The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2021

Filed:

May. 09, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Kangguo Cheng, Schenectady, NY (US);

Christopher J. Waskiewicz, Rexford, NY (US);

Michael P. Belyansky, Halfmoon, NY (US);

Brent Alan Anderson, Jericho, VT (US);

Muthumanickam Sankarapandian, Niskayuna, NY (US);

Puneet Suvarna, Albany, NY (US);

Hiroaki Niimi, Cahoes, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 21/02 (2006.01); H01L 29/417 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6656 (2013.01); H01L 21/0217 (2013.01); H01L 21/0228 (2013.01); H01L 21/02164 (2013.01); H01L 21/02271 (2013.01); H01L 21/31111 (2013.01); H01L 29/1037 (2013.01); H01L 29/41741 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01);
Abstract

An integrated semiconductor device having a substrate and a vertical field-effect transistor (FET) disposed on the substrate. The vertical FET includes a fin and a bottom spacer. The bottom spacer further includes a first spacer layer and a second spacer layer formed on top of the first spacer layer. The bottom spacer provides for a symmetrical straight alignment at a bottom junction between the bottom spacer and the fin.


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