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Mei-Ling Chen

USPTO Granted Patents = 18 (Patent Applications = 2)

Average Co-Inventor Count = 4.7

ph-index = 5

Forward Citations = 53(Granted Patents)

Location History:

Hsinchu Hsien, TW (2001)
Kaoshiung, TW (2003)
Hsinchu County, TW (2013 - 2015)
Hsin-Chu, TW (2014 - 2016)
Kao-Hsiung, TW (2008 - 2019)

Company Filing History:

9 out of 40,739

Taiwan Semiconductor Manufacturing Comp. Ltd.

patents

9 out of 7,082

United Microelectronics Corp.

patents

2 out of 351

Fujian Jinhua Integrated Circuit Co., Ltd.

patents

where one patent can have more than one assignee

Years Active: 2001-2019

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18 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 10312080 - Method for forming amorphous silicon multuple layer structure (2019-06-04),

2. 10262895 - Method for forming semiconductor device (2019-04-16),

3. 9812390 - Semiconductor devices including conductive features with capping layers and methods of forming the same (2017-11-07),

4. 9640428 - Self-aligned repairing process for barrier layer (2017-05-02),

5. 9514928 - Selective repairing process for barrier layer (2016-12-06),

6. 9349689 - Semiconductor devices including conductive features with capping layers and methods of forming the same (2016-05-24),

7. 9324606 - Self-aligned repairing process for barrier layer (2016-04-26),

8. 9004914 - Method of and apparatus for active energy assist baking (2015-04-14),

9. 8877083 - Surface treatment in the formation of interconnect structure (2014-11-04),

10. 8481412 - Method of and apparatus for active energy assist baking (2013-07-09),

11. 8350246 - Structure of porous low-k layer and interconnect structure (2013-01-08),

12. 8092861 - Method of fabricating an ultra dielectric constant (K) dielectric layer (2012-01-10),

13. 8084357 - Method for manufacturing a dual damascene opening comprising a trench opening and a via opening (2011-12-27),

14. 7947565 - Forming method of porous low-k layer and interconnect process (2011-05-24),

15. 7851030 - Method of reducing number of particles on low-k material layer (2010-12-14),

Title: Mei-Ling Chen: Innovator in Semiconductor Technology

Introduction

Mei-Ling Chen is a prominent inventor based in Kaohsiung, Taiwan. She has made significant contributions to the field of semiconductor technology, holding a total of 18 patents. Her innovative work has advanced the development of semiconductor devices and materials.

Latest Patents

Among her latest patents is a method for forming an amorphous silicon multiple layer structure. This invention outlines a process that begins with providing a substrate material layer, followed by the formation of a first amorphous silicon layer that contains hydrogen atoms. An ultraviolet curing process is then applied to remove these hydrogen atoms, culminating in the formation of a second amorphous silicon layer on top of the first. Another notable patent is a method for fabricating a semiconductor device. This invention details the steps of providing a substrate with defined memory and peripheral regions, forming insulating layers through atomic layer deposition, and establishing a contact structure to connect the components electrically.

Career Highlights

Mei-Ling Chen has worked with leading companies in the semiconductor industry, including Taiwan Semiconductor Manufacturing Company Ltd. and United Microelectronics Corporation. Her experience in these organizations has allowed her to refine her skills and contribute to groundbreaking advancements in semiconductor technology.

Collaborations

Throughout her career, Mei-Ling has collaborated with notable colleagues such as Joung-Wei Liou and Chung-Chi Ko. These partnerships have fostered innovation and have been instrumental in her research and development efforts.

Conclusion

Mei-Ling Chen's contributions to semiconductor technology through her patents and collaborations highlight her role as a leading inventor in the field. Her work continues to influence advancements in technology and materials science.

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