Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Mei-Ling Chen

Chung-Chi Ko

Joung-Wei Liou

Keng-Chu Lin

Su-Jen Sung

Ching-Hua Hsieh

Chien-Chung Huang

Chih-Chien Chi

Kuo-Chih Lai

Yu-Tsung Lai

Huang-Yi Huang

Szu-Ping Tung

Shwang-Ming Jeng

Hui-Chun Yang

Yi-Wei Chen

Shih-Fang Tzou

Wei-Hsin Liu

Chia-Lung Chang

Chia Cheng Chou

Tzu-Chin Wu

Jui-Min Lee

Ching-Hsiang Chang

Chih-Chien Liu

Po-Cheng Shih

Chia-Cheng Chou

Jei-Ming Chen

Chen-Fa Lu

Chun-Jen Huang

Chin-Hsiung Ho

Wei-Chih Chen

Cheng-Ming Weng

Miao-Chun Lin

Li-Chung Lee

Chun-Chieh Huang

Patrick Cheng

Feng-Yu Hsu

Liang-Kun Huang

Chung-Hsien Kao

Jiann-Jen Chiou

The present invention provides a method for forming an amorphous silicon multiple layer structure, the method comprises the flowing steps: first, a substrate material layer is provided, next, a first amorphous silicon layer is formed on the substrate material layer, wherein the first amorphous silicon layer includes a plurality of hydrogen atoms disposed therein, afterwards, an UV curing process is performed to the first amorphous silicon layer, so as to remove the hydrogen atoms from the first amorphous silicon layer, finally, a second amorphous silicon layer is formed on the first amorphous silicon layer.

Method for forming amorphous silicon multuple layer structure

The present invention provides a method for fabricating a semiconductor device, comprising at least the steps of: providing a substrate in which a memory region and a peripheral region are defined, the memory region includes a plurality of memory cells, each memory cell includes at least a first transistor and a capacitor, the peripheral region compress a second transistor, a first insulating layer is formed within the memory region and the peripheral region by an atomic layer deposition process, covering the capacitor of the memory cells in the memory region and the second transistor in the peripheral region, and a second insulating layer is formed, overlying the first insulating layer and the peripheral region. Finally, a contact structure is formed within the second insulating layer, and electrically connecting the second transistor.

Method for forming semiconductor device

Semiconductor devices, methods of manufacture thereof, and methods of forming conductive features thereof are disclosed. A semiconductor device includes an insulating material layer disposed over a workpiece. The insulating material layer includes a silicon-containing material comprising about 13% or greater of carbon (C). A conductive feature is disposed within the insulating material layer. The conductive feature includes a capping layer disposed on a top surface thereof.

Semiconductor devices including conductive features with capping layers and methods of forming the same

A self-aligned repairing process for a barrier layer is provided. A repair layer is formed by chemical vapor deposition using an organometallic compound as a precursor gas. The precursor gas adsorbed on a dielectric layer exposed by defects in a barrier layer is transformed to an insulating metal oxide layer, and the precursor gas adsorbed on the barrier layer is transformed to a metal layer.

Self-aligned repairing process for barrier layer

A selectively repairing process for a barrier layer is provided. A repair layer is formed by chemical vapor deposition using an organosilicon compound as a precursor gas. The precursor gas adsorbed on a low-k dielectric layer exposed by defects in a barrier layer is transformed to a porous silicon oxide layer has a density more than the density of the low-k dielectric layer.

Selective repairing process for barrier layer

An Active Energy Assist (AEA) baking chamber includes an AEA light source assembly and a heater pedestal. The AEA baking chamber further includes a controller for controlling a power input to the AEA light source assembly and a power input to the heater pedestal. A method of forming interconnects on a substrate includes etching a substrate and wet cleaning the etched substrate. The method further includes active energy assist (AEA) baking the substrate after the wet-cleaning. The AEA baking includes placing the substrate on a heater pedestal in an AEA chamber, exposing the substrate to light having a wavelength equal to or greater than 400 nm, wherein said light is emitted by a light source and controlling the light source and the heater pedestal using a controller.

Method of and apparatus for active energy assist baking

A Ultra-Violet (UV) treatment is performed on an exposed surface of a low-k dielectric layer and an exposed surface of a metal line. After the UV treatment, an organo-metallic soak process is performed on the exposed surface of the low-k dielectric layer and the exposed surface of the metal line. The organo-metallic soak process is performed using a process gas including a metal bonded to an organic group.

Surface treatment in the formation of interconnect structure

A method of and apparatus for forming interconnects on a substrate includes etching patterns in ultra-low k dielectric and removing moisture from the ultra-low k dielectric using active energy assist baking. During active energy assist baking, the ultra-low k dielectric is heated and exposed to light having only wavelengths greater than 400 nm for about 1 to about 20 minutes at a temperature of about 300 to about 400 degrees Celsius. The active energy assist baking is performed after wet-cleaning or after chemical mechanical polishing, or both.

A structure of a porous low-k layer is described, comprising a bottom portion and a body portion of the same atomic composition, wherein the body portion is located on the bottom portion, and the bottom portion has a density higher than the density of the body portion. An interconnect structure is also described, including the above porous low-k layer, and a conductive layer filling up a damascene opening in the porous low-k layer.

Structure of porous low-k layer and interconnect structure

A fabrication method of an ultra low-k dielectric layer is provided. A deposition process is performed, under the control of a temperature varying program or a pressure varying program, by reacting a dielectric matrix to form porous low-k dielectric layers with a gradient density on a barrier layer over a substrate.

Method of fabricating an ultra dielectric constant (K) dielectric layer

A method for manufacturing a multi cap layer includes providing a substrate, forming a multi cap layer comprising a first cap layer and a second cap layer formed thereon on the substrate, forming a patterned metal hard mask layer on the multi cap layer, and performing an etching process to etch the multi cap layer through the patterned hard mask layer and to form an opening in the second cap layer.

Method for manufacturing a dual damascene opening comprising a trench opening and a via opening

A method of forming a porous low-k layer is described. A CVD process is conducted to a substrate, wherein a framework precursor and a porogen precursor are supplied. In an end period of the supply of the framework precursor, the value of at least one deposition parameter negatively correlated with the density of the product of the CVD process is decreased.

Forming method of porous low-k layer and interconnect process

A method of reducing the number of particles on a low-k material layer is described. The low-k material layer is formed by a plasma enhanced chemical vapor deposition process, wherein a reaction gas, a cleaning gas, a high-frequency power and a low-frequency power are used. The method includes turning off the reaction gas and the low-frequency power after the low-k material layer is formed, and continuing to provide the cleaning gas during a delay time.

Method of reducing number of particles on low-k material layer

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Kaohsiung, Taiwan

Mei-Ling Chen