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For the Inventor, By the Inventor

Duerrroehrsdorf-Dittersbach, Germany

Manfred Horstmann

USPTO Granted Patents = 83 


Average Co-Inventor Count = 3.4

ph-index = 13

Forward Citations = 948(Granted Patents)

Forward Citations (Not Self Cited) = 944(Oct 12, 2025)


Inventors with similar research interests:


Location History:

  • Dresde, DE (2001)
  • Dürrersdorf-Diltersbach, DE (2005)
  • Dürrersdorf-Dittersbach, DE (2006)
  • Duerrrohrsdorf-Dittersbach, DE (2008)
  • Dresden, DE (2000 - 2009)
  • Duehrrroersdorf-Dittersbach, DE (2009)
  • Duemroehrsdorf-Dittersbach, DE (2009)
  • Duerrrhoerhrsdorf-Dittersbach, DE (2010)
  • Duerrrhoehrsdorf-Dittersbach, DE (2008 - 2011)
  • Duerroehrsdorf-Dittersbach, DE (2006 - 2012)
  • Duerrrhoehrsdorf-Ditterbach, DE (2008 - 2012)
  • Duerrroehrsdorf-Dittersbach, DE (2007 - 2013)

Company Filing History:

goldMedal74 out of 12,867 
 
Advanced Micro Devices Corporation
 patents
silverMedal9 out of 5,671 
 
Globalfoundries Inc.
 patents

Years Active: 2000-2013

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83 patents (USPTO):
1. 8440516 - Method of forming a field effect transistor (2013-05-14),
2. 8288256 - Enhancing transistor characteristics by a late deep implantation in combination with a diffusion-free anneal process (2012-10-16),
3. 8274120 - Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions (2012-09-25),
4. 8188871 - Drive current adjustment for transistors by local gate engineering (2012-05-29),
5. 8138571 - Semiconductor device comprising isolation trenches inducing different types of strain (2012-03-20),
6. 8101512 - Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topography (2012-01-24),
7. 8097542 - Etch stop layer of reduced thickness for patterning a dielectric material in a contact level of closely spaced transistors (2012-01-17),
8. 8039338 - Method for reducing defects of gate of CMOS devices during cleaning processes by modifying a parasitic PN junction (2011-10-18),
9. 8039335 - Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain (2011-10-18),
10. 7999326 - Tensile strain source using silicon/germanium in globally strained silicon (2011-08-16),
11. 7955937 - Method for manufacturing semiconductor device comprising SOI transistors and bulk transistors (2011-06-07),
12. 7906383 - Stress transfer in an interlayer dielectric by providing a stressed dielectric layer above a stress-neutral dielectric material in a semiconductor device (2011-03-15),
13. 7893503 - Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain (2011-02-22),
14. 7863171 - SOI transistor having a reduced body potential and a method of forming the same (2011-01-04),
15. 7829421 - SOI transistor having an embedded strain layer and a reduced floating body effect and a method for forming the same (2010-11-09),

Title: Manfred Horstmann: Innovator in Semiconductor Technology

Introduction

Manfred Horstmann, based in Duerrroehrsdorf-Dittersbach, Germany, is a prolific inventor with an impressive portfolio of 83 patents. His work primarily focuses on advancements in semiconductor technology, particularly methods for designing field effect transistors that enhance their performance and efficiency.

Latest Patents

Among his most recent innovations, Horstmann's patents include a novel method of forming a field effect transistor. This process involves using a substrate that comprises a biaxially strained layer of semiconductor material. The method details the formation of a gate electrode situated on this strained layer, alongside the creation of raised source and drain regions adjacent to the gate. Furthermore, the introduction of dopant ions into these regions forms extended source and drain regions, optimizing the transistor's performance. Another groundbreaking patent discusses enhancing transistor characteristics through a late deep implantation method, coupled with a diffusion-free anneal process, which significantly improves device efficiency and reduces parasitic capacitance.

Career Highlights

Horstmann has contributed significantly to the semiconductor industry through his roles at leading companies. He has worked for Advanced Micro Devices Corporation and Globalfoundries Inc., where he applied his expertise in developing innovative semiconductor solutions. His contributions have not only advanced the technology but also paved the way for more efficient manufacturing processes in the industry.

Collaborations

Throughout his career, Manfred Horstmann has collaborated with notable professionals, including Karsten Wieczorek and Rolf Stephan. These partnerships have proven fruitful in pushing the boundaries of semiconductor research and development, leading to numerous patents and advancements.

Conclusion

Manfred Horstmann's contributions to the field of semiconductor technology are indicative of his innovative spirit and commitment to enhancing electronic devices. His vast experience and collaborative efforts have positioned him as a key figure in advancing transistor technology, influencing both the industry and upcoming inventors in this space.

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