South Burlington, VT, United States of America

Leendert M Huisman

This inventor holds 24 USPTO granted patents, primarily in Semiconductor Diagnostics. Top assignee: International Business Machines Corporation. Active years: 1988-2011.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Leendert M Huisman. Retrieved from https://idiyas.com/inventor/leendert-m-huisman

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 24

% Patents Active = 41.7

Average Co-Inventor Count = 3.7

ph-index = 10

Forward Citations = 255(Granted Patents)

Location History:

Ossining, NY (US) (1988)
Peekskill, NY (US) (1994)
South Burlington, VT (US) (2000 - 2011)

Company Filing History:

24 out of 166,351

International Business Machines Corporation

patents

Years Active: 1988-2011

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Areas of Expertise:

Scan Chain Testing

Defect Diagnosis

VLSI Manufacturing

Fault Isolation

Dynamic Reconfiguration

Logic Circuit Failures

Test Data Storage

Diagnostic Data Collection

Embedded Objects Analysis

Process Defects

Combinational Logic

Random Test Pattern Generator

24 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 7895487 - Scan chain diagnostics using logic paths (2011-02-22),

2. 7752514 - Methods and apparatus for testing a scan chain to isolate defects (2010-07-06),

3. 7558999 - Learning based logic diagnosis (2009-07-07),

4. 7434130 - Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection (2008-10-07),

5. 7313744 - Methods and apparatus for testing a scan chain to isolate defects (2007-12-25),

6. 7240261 - Scan chain diagnostics using logic paths (2007-07-03),

7. 7230335 - Inspection methods and structures for visualizing and/or detecting specific chip structures (2007-06-12),

8. 7194706 - Designing scan chains with specific parameter sensitivities to identify process defects (2007-03-20),

9. 7139950 - Segmented scan chains with dynamic reconfigurations (2006-11-21),

10. 7089514 - Defect diagnosis for semiconductor integrated circuits (2006-08-08),

11. 6954916 - Methodology for fixing Qcrit at design timing impact (2005-10-11),

12. 6931580 - Rapid fail analysis of embedded objects (2005-08-16),

13. 6901542 - Internal cache for on chip test data storage (2005-05-31),

14. 6880136 - Method to detect systematic defects in VLSI manufacturing (2005-04-12),

15. 6865501 - Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection (2005-03-08),

Title: The Innovative Journey of Inventor Leendert M Huisman

Introduction: Leendert M Huisman, a talented male inventor hailing from South Burlington, VT (US), has made significant contributions to the world of innovations and patents.

Latest Patents: Leendert M Huisman holds several patents in various fields, showcasing his diverse range of expertise and creativity.

Career Highlights: Throughout his illustrious career, Leendert M Huisman has been recognized for his groundbreaking inventions that have had a lasting impact on industries such as technology, healthcare, and sustainability.

Collaborations: Leendert M Huisman has collaborated with leading companies, research institutions, and universities to further develop and commercialize his inventions, demonstrating his ability to work effectively in multidisciplinary teams.

Conclusion: In conclusion, Leendert M Huisman's innovative spirit, coupled with his dedication to pushing the boundaries of what is possible, has solidified his reputation as a pioneering inventor in the world of patents and innovations.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]