International Business Machines Corporation

Leendert M Huisman

Franco Motika

William Vincent Huott

Leah M P Pastel

Leah M Pastel

Maroun Kassab

Leah M Pfeifer Pastel

James William Adkisson

John Maxwell Cohn

Phillip J Nigh

Thomas Webster Bartenstein

Douglas C Heaberlin

David E Sweenor

David P Vallett

Thomas Gregory Sopchak

Glen E Richard

Raymond J Rosner

Greg Bazan

Kevin C Quandt

Kevin J Barcomb

Steven J Holmes

Mark David Jaffe

Kerry Bernstein

Philip George Emma

Norman Jay Rohrer

Cherie Renee Kagan

Paul David Kartschoke

Thomas W Williams

Daniel Ray Knebel

Matthew Sean Grady

Sandip Kundu

Paul William Pastel

Pia Naoko Sanda

Matthias Gruetzner

Mark Alan Erle

Cordt W Starke

L Owen Farnsworth

Jerome L Cann

John L Carter

Francis Woytowich

James R Salimeno, Iii

Edward E Horton, Iii

Xiaodong Xiao

Matthew Christopher Graf

Ya-Chieh Lai

Zaifu Zhang

Francis Gravel

Kenneth Rowe

Mark F Olive

Thomas F Mechler

A structure and method for optimzing scan chain fail disgnosis. First, logic paths from target latches in a target scan chain to observation latches in at least one other observation scan chain are identified. Then, the locations of the observation latches within the other scan chains are optimized.

Scan chain diagnostics using logic paths

Systems, methods and apparatus are provided for isolating a defect in a scan chain. The invention includes modifying a first test mode of a plurality of latches included in a scan chain, operating the latches in the modified first test mode, and operating the plurality of latches included in the scan chain in a second test mode. A portion of the scan chain adjacent and following a stuck-@-0 or stuck-@-1 fault in the scan chain may store and/or output a value complementary to the value on the output of the previous portion of the scan chain due to the fault. Such values may be unloaded from the scan chain and used for diagnosing (e.g., isolating a defect in) the defective scan chain. Numerous other aspects are provided.

Methods and apparatus for testing a scan chain to isolate defects

A system and method for diagnosing a failure in an electronic device. A disclosed system comprises: a defect table that associates previously studied features with known failures; and a fault isolation system that compares an inputted set of suspected faulty device features with the previously studied features listed in the defect table in order to identify causes of the failure.

Learning based logic diagnosis

In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.

Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection

A structure and method for performing scan chain diagnosis. The structure comprises a diagnosed/target scan chain and one or more good observation scan chains. Observing logic paths from the target scan chain to observation scan chains can be identified according to a pre-specified criterion. The diagnosed scan chain is loaded in series with a test pattern. Then, the contents of the observed latch(es) in the diagnosed scan chain propagate through the observing logic paths. Then, the output signals of the observing logic paths are strobed into the observing latch(es) in the observing scan chain(s). Then, the observing scan chain(s) are unloaded and the contents of the observing latch(es) are collected and analyzed to determine the defect types and the defect ranges in the diagnosed scan chain.

The present invention provides inspection methods and structures for facilitating the visualization and/or detection of specific chip structures. Optical or fluorescent labeling techniques are used to 'stain' a specific chip structure for easier detection of the structure. Also, a temporary/sacrificial illuminating (e.g., fluorescent) film is added to the semiconductor process to facilitate the detection of a specific chip structure. Further, a specific chip structure is doped with a fluorescent material during the semiconductor process. A method of the present invention comprises: providing a first and a second material; processing the first material to form a portion of a semiconductor structure; and detecting a condition of the second material to determine whether processing of the first material is complete.

Inspection methods and structures for visualizing and/or detecting specific chip structures

A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.

Designing scan chains with specific parameter sensitivities to identify process defects

A method is disclosed of diagnosing defects in scan chains by statically and dynamically segmenting and reconfiguring the scan chains. A plurality of serially extending scan chains are partitioned into a plurality of serially arranged equal length segments such that each serially extending scan chain comprises a plurality of serially extending segments. A plurality of multiplexors are positioned between the plurality of segments of each scan chain, and are controlled and utilized to connect each segment of the scan chain to the next serial segment in the same scan chain, or to connect each segment of the scan chain to the next serial segment in a lateral adjacent scan chain. Scan in data patterns are introduced into the plurality of serially extending scan chains. Particular defective segments of the plurality of serially extending scan chains are identified by controlling the multiplexors to connect and shift the data pattern out of each segment of a scan chain serially to the next serial segment in the same scan chain, or to connect and shift the data pattern out of each segment of the scan chain to the next serial segment in an adjacent lateral scan chain, with a sequence of serial shifts and serial-lateral shifts being selected to identify particular defective segments of the plurality of serially extending scan chains.

Segmented scan chains with dynamic reconfigurations

A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.

Defect diagnosis for semiconductor integrated circuits

A method and system for simulating an integrated circuit. The method includes the steps of performing a timing analysis of the circuits to ensure that they meet specified timing criteria, performing soft error analysis of the circuits to determine whether they meet specified soft error criteria, and improving those circuits that fail the soft error analysis to improve their resistance to soft errors and having no degradation on timing. Preferably, the improving step includes the step of improving those circuits that fail the soft error analysis by either having an additional voltage source or altering the capacitance of the circuits.

Methodology for fixing Qcrit at design timing impact

A method for analyzing test data for objects on an IC or a wafer is provided. The test data is linked to available layout information about the object under test. Certain objects are selected based on the test data. A representation of the selected objects is placed on a map of the IC or on a map of the wafer. The representation should correspond to the physical location of the object on the IC or wafer. Preferably, the representation comprises one or more polygons that enclose all devices that make up the object.

Rapid fail analysis of embedded objects

A method of testing a semiconductor device having a memory is disclosed. The method includes selecting a portion of the memory; testing the selected portion of the memory; designating the selected portion of the memory as a designated memory in response to an acceptable testing result; and storing data in the designated portion of the memory for retrieval at a later time. Provision for soft repair of the selected memory is made. Test data can be compressed before being stored in the designated memory.

Internal cache for on chip test data storage

Defects in manufacturing of IC devices are analyzed by testing the devices for defects using results of LSSD technology to find at least one failing pattern that contains incorrect values. The failing latches are used as a starting point to trace back through combinational logic feeding the failing latches, until controllable latches are encountered. A decision is then made to continue the back tracing or not depending on whether the latter latches were clocked during the application of one of the failing patterns or not.

Method to detect systematic defects in VLSI manufacturing

Growing community of inventors

South Burlington, VT, United States of America

Leendert M Huisman