The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6865501 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 08, 2005

Filed:

Oct. 30, 2003
Applicants:

Leendert M. Huisman, South Burlington, VT (US);

William V. Huott, Holmes, NY (US);

Franco Motika, Hopewell Junction, NY (US);

Leah M. Pfeifer Pastel, Essex, VT (US);

Inventors:

Leendert M. Huisman, South Burlington, VT (US);

William V. Huott, Holmes, NY (US);

Franco Motika, Hopewell Junction, NY (US);

Leah M. Pfeifer Pastel, Essex, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F019/00 ;
U.S. Cl.
CPC ...
Abstract

In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.


Find Patent Forward Citations

Huisman, Leendert. (2005). Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection (U.S. Patent No. 6865501). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6865501

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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