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For the Inventor, By the Inventor

San Jose, CA, United States of America

Kuoyuan (Peter) Hsu

This inventor holds 81 USPTO granted patents and 2 published patent applications, primarily in Memory Circuit Design (CPC class G11C11-419). Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2009-2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kuoyuan (Peter) Hsu. Retrieved from https://idiyas.com/inventor/kuoyuan-peter-hsu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 81 

% Patents Active = 59.3

Average Co-Inventor Count = 2.7

ph-index = 7

Forward Citations = 565(Granted Patents)

Forward Citations (Not Self Cited) = 509(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • San Jose, CA (US) (2009 - 2021)
  • Hsinchu, TW (2016 - 2022)

Company Filing History:

goldMedal81 out of 42,872 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 2009-2022

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Areas of Expertise:
Memory Circuit
Latch-Up Prevention
Tracking Mechanisms
Integrated Circuits
Memory Layout
Data Retention
Voltage Boosting
Error Correction
3D Integrated Circuit
Memory Array
SRAM
Semiconductor Memory
81 patents (USPTO):Explore Patents
1. 11443786 - Memory circuit including tracking circuit (2022-09-13),
2. 11145335 - Latch-up prevention circuit for memory storage system (2021-10-12),
3. 11024621 - Memory circuit layout method (2021-06-01),
4. 11017825 - Memory circuit including tracking circuit (2021-05-25),
5. 10878852 - Latch-up prevention circuit for memory storage system (2020-12-29),
6. 10553265 - Memory circuit having tracking circuit including series-connected transistors (2020-02-04),
7. 10490544 - Memory circuit layout (2019-11-26),
8. 10424587 - Memory metal scheme (2019-09-24),
9. 10163476 - Method of operating tracking circuit (2018-12-25),
10. 9978446 - Memory with regulated ground nodes and method of retaining data therein (2018-05-22),
11. 9966378 - Integrated circuit structure (2018-05-08),
12. 9934833 - Memory circuit having tracking circuit including series-connected transistors (2018-04-03),
13. 9887186 - Memory circuit, layout of memory circuit, and method of forming layout (2018-02-06),
14. 9818752 - Memory metal scheme (2017-11-14),
15. 9812177 - Circuit, method of using the circuit and memory macro including the circuit (2017-11-07),

Title: Top Inventor in San Jose

Introduction: Shan Liu is recognized as a leading inventor in San Jose, contributing significantly to various technological advancements.

Latest Patents: Shan Liu holds several patents that showcase innovative solutions in his field.

Career Highlights: Throughout his career, Liu has achieved numerous milestones that highlight his expertise and impact on technology.

Collaborations: He has worked with various organizations and teams, fostering collaboration to drive innovation.

Conclusion: Shan Liu's contributions continue to shape the landscape of technology in San Jose and beyond.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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