The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2018

Filed:

Dec. 14, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Kuoyuan (Peter) Hsu, San Jose, CA (US);

Yukit Tang, Sunnyvale, CA (US);

Derek Tao, Fremont, CA (US);

Young Seog Kim, Pleasanton, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 11/419 (2006.01); G11C 11/413 (2006.01); G11C 7/00 (2006.01); H01L 27/11 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 7/00 (2013.01); G11C 11/413 (2013.01); H01L 27/11 (2013.01);
Abstract

A memory device includes: memory cells arranged in rows and columns; and regulated ground circuits corresponding to the columns. Each regulated ground circuit includes: a column ground node; at least three low-side voltage sources; at least three switches, each of the at least three switches being coupled between the column ground node and a corresponding one of the at least three voltage sources; and each of the at least three switches being controlled by a corresponding one of different control signals; Each memory cell includes: a high-side voltage source; an internal ground node coupled to the column ground node; and a cross latch having output and output_bar nodes. The cross latch is coupled between the high-side voltage source and the internal ground node, and is configured to selectively connect the output and output_bar nodes to corresponding bit and bit_bar lines.


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