Kanagawa, Japan

Kishou Kaneko

This inventor holds 31 USPTO granted patents and 7 published patent applications, primarily in Semiconductor Devices. Top assignee: Renesas Electronics Corporation. Active years: 2011-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kishou Kaneko. Retrieved from https://idiyas.com/inventor/kishou-kaneko

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 31 

% Patents Active = 58.1

Average Co-Inventor Count = 3.2

ph-index = 7

Forward Citations = 266(Granted Patents)


Location History:

  • Kawasaki, JP (2015 - 2016)
  • Kanagawa, JP (2011 - 2017)
  • Tokyo, JP (2016 - 2017)

Company Filing History:


Years Active: 2011-2017

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Areas of Expertise:
Semiconductor Device
Manufacturing Method
Electro-Static Discharge
Multi-Layered Interconnect
Bottom Gate Transistor
SiP Device
Wiring Via
Switch Via
Semiconductor Apparatus
Transistor
Interconnect Structure
Device Protection
31 patents (USPTO):Explore Patents

Title: Innovations in Semiconductor Technology: The Contributions of Kishou Kaneko

Introduction: Kishou Kaneko, based in Kanagawa, Japan, is a notable inventor with an impressive portfolio of 31 patents. His work primarily focuses on semiconductor technology, which is crucial for advancements in electronics. Kaneko's innovative methodologies have led to significant improvements in the performance and manufacturing processes of semiconductor devices.

Latest Patents: Kaneko's recent patents include a groundbreaking semiconductor device and a new method for manufacturing these devices. One of his inventions describes a method involving the preparation of a semiconductor substrate, the formation of a first insulating layer, and the creation of first grooves within this layer. This process further includes the integration of gate electrodes and interconnects made of copper or copper alloys, enhancing electrical conductivity. Another notable patent details the design of an in-wiring-layer active element, which facilitates electrical isolation between the gate electrode and the channel in a top gate structure. This configuration significantly improves the operational efficiency of semiconductor devices.

Career Highlights: Kaneko has made a substantial impact on the semiconductor industry through his work at Renesas Electronics Corporation. His role in developing technologies that streamline semiconductor manufacturing processes showcases his expertise and innovative thinking. His patents not only exemplify his technical skills but also his commitment to pushing the boundaries of what is possible in semiconductor technology.

Collaborations: Throughout his career, Kishou Kaneko has collaborated with talented colleagues like Yoshihiro Hayashi and Naoya Inoue. These partnerships have fostered a collaborative environment that encourages innovation and the sharing of ideas, further enhancing the quality of their contributions to the field.

Conclusion: Kishou Kaneko's contributions to semiconductor technology are significant and reflect a deep understanding of the industry's needs. With numerous patents to his name, his work at Renesas Electronics Corporation continues to influence the future of electronics. Kaneko's innovative spirit and collaborative efforts underscore the importance of teamwork in driving technological advancement.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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