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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9349844 B1

PDFFull Text
Date of Patent:
May. 24, 2016

Filed:

Oct. 29, 2014

Semiconductor device manufacturing method

Applicant:

Renesas Electronics Corporation, Kanagawa, JP;

Inventors:

Naoya Inoue, Kanagawa, JP;

Kishou Kaneko, Kanagawa, JP;

Yoshihiro Hayashi, Kanagawa, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Kanagawa, JP;

Attorney:

Young & Thompson

Primary Examiner:

Marc Armand

Assistant Examiner:

Quinton Brasfield

Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/12 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 23/522 (2006.01); H01L 29/423 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 29/786 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66969 (2013.01); H01L 21/0217 (2013.01); H01L 21/02167 (2013.01); H01L 21/02565 (2013.01); H01L 21/76829 (2013.01); H01L 21/76877 (2013.01); H01L 23/522 (2013.01); H01L 23/5329 (2013.01); H01L 23/53295 (2013.01); H01L 27/124 (2013.01); H01L 27/1225 (2013.01); H01L 29/42384 (2013.01); H01L 29/7869 (2013.01); H01L 29/78606 (2013.01); H01L 2924/0002 (2013.01);
Abstract

The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer. A diffusion prevention film is formed between the first wiring layer and a second wiring layer. A gate insulation film is formed by: forming a recess over the upper face of the diffusion prevention film in the region overlapping with the gate electrode and around the region; and thinning the part.

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