The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2016

Filed:

Jan. 14, 2016
Applicant:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Inventors:

Kishou Kaneko, Tokyo, JP;

Naoya Inoue, Tokyo, JP;

Yoshihiro Hayashi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 27/02 (2006.01); H01L 27/06 (2006.01); H01L 27/12 (2006.01); H01L 29/24 (2006.01); H01L 29/786 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0285 (2013.01); H01L 23/552 (2013.01); H01L 27/0255 (2013.01); H01L 27/0296 (2013.01); H01L 27/0688 (2013.01); H01L 27/124 (2013.01); H01L 27/1218 (2013.01); H01L 27/1225 (2013.01); H01L 29/24 (2013.01); H01L 29/7869 (2013.01); H01L 23/522 (2013.01); H01L 23/5283 (2013.01); H01L 23/53295 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor device includes a semiconductor substrate on which a semiconductor device is formed; first and second pads; a first insulating film which is formed above the semiconductor substrate; a plurality of wiring lines which are embedded in ditches provided in the first insulating film; a second insulating film provided to cover the first insulating film and the plurality of wiring lines; a semiconductor layer formed on the second insulating film; a source electrode connected with the semiconductor layer; and a drain electrode connected with the semiconductor layer. The plurality of wiring lines includes a gate electrode provided in a position which is opposite to the semiconductor layer. The semiconductor layer, the source electrode, the drain electrode and the gate electrode configure an ESD protection device to discharge a current by ESD surge from the first pad to the second pad.


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