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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9312394 B1

PDFFull Text
Date of Patent:
Apr. 12, 2016

Filed:

Jun. 19, 2015

Semiconductor device and method of manufacturing semiconductor device

Applicant:

Renesas Electronics Corporation, Kawasaki-shi, JP;

Inventors:

Yoshihiro Hayashi, Kawasaki, JP;

Naoya Inoue, Kawasaki, JP;

Kishou Kaneko, Kawasaki, JP;

Assignee:

Renesas Electronics Corporation, Kawasaki-Shi, Kanagawa, JP;

Attorney:

McGinn IP Law Group, PLLC

Primary Examiner:

Long K Tran

Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/786 (2006.01); H01L 21/28 (2006.01); H01L 27/12 (2006.01); H01L 29/423 (2006.01); H01L 29/792 (2006.01); H01L 29/41 (2006.01); H01L 29/24 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7869 (2013.01); H01L 21/28282 (2013.01); H01L 27/124 (2013.01); H01L 27/1225 (2013.01); H01L 29/24 (2013.01); H01L 29/41 (2013.01); H01L 29/42344 (2013.01); H01L 29/42352 (2013.01); H01L 29/495 (2013.01); H01L 29/4908 (2013.01); H01L 29/4966 (2013.01); H01L 29/518 (2013.01); H01L 29/78648 (2013.01); H01L 29/792 (2013.01); H01L 29/242 (2013.01);
Abstract

A semiconductor device including a semiconductor substrate, a first insulating layer formed over said semiconductor substrate, first grooves formed in said first insulating layer, a gate electrode and a first interconnect filled in said first grooves, respectively, a gate insulating film formed over said gate electrode, a semiconductor layer formed over said gate insulating, a second insulating layer formed over said semiconductor layer and said first insulating film, a via formed in said second insulating layer and connected to said semiconductor layer, a second groove formed in said second insulating layer, and a second interconnect filled in said second groove, formed over said via and connected to said via.

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