The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2017

Filed:

Mar. 31, 2016
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Yoshihiro Hayashi, Tokyo, JP;

Naoya Inoue, Tokyo, JP;

Kishou Kaneko, Tokyo, JP;

Assignee:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/768 (2006.01); H01L 21/28 (2006.01); H01L 27/12 (2006.01); H01L 29/423 (2006.01); H01L 29/792 (2006.01); H01L 29/41 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 29/24 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76807 (2013.01); H01L 21/28282 (2013.01); H01L 21/76877 (2013.01); H01L 27/124 (2013.01); H01L 27/1225 (2013.01); H01L 29/24 (2013.01); H01L 29/41 (2013.01); H01L 29/42344 (2013.01); H01L 29/42352 (2013.01); H01L 29/495 (2013.01); H01L 29/4908 (2013.01); H01L 29/4966 (2013.01); H01L 29/518 (2013.01); H01L 29/66757 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78648 (2013.01); H01L 29/792 (2013.01); H01L 29/242 (2013.01);
Abstract

The method of manufacturing a semiconductor device, including preparing a semiconductor substrate, forming a first insulating layer over said semiconductor substrate, forming first grooves in the first insulating film, forming a gate electrode and a first interconnect in the first grooves, respectively, forming a gate insulating film over the gate electrode, forming a semiconductor layer over the gate insulating, forming a second insulating layer over the semiconductor layer and the first insulating film, forming a via in the second insulating layer, and forming a second interconnect such that the second interconnect is connected to the semiconductor layer through the via. The gate electrode, the first interconnect and the second interconnect are formed by Cu or Cu alloy, respectively.


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