IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9496403 B1

PDFFull Text
Date of Patent:
Nov. 15, 2016

Filed:

Dec. 10, 2012

Semiconductor device and method of manufacturing the same

Applicant:

Renesas Electronics Corporation, Kanagawa, JP;

Inventors:

Kishou Kaneko, Kanagawa, JP;

Hiroshi Sunamura, Kanagawa, JP;

Yoshihiro Hayashi, Kanagawa, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Kanagawa, JP;

Attorney:

Young & Thompson

Primary Examiner:

Cuong B Nguyen

Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 27/02 (2006.01); H01L 49/02 (2006.01); H03K 19/00 (2006.01); H01L 27/06 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 29/786 (2013.01); H01L 27/0207 (2013.01); H01L 27/0629 (2013.01); H01L 27/0688 (2013.01); H01L 27/088 (2013.01); H01L 27/12 (2013.01); H01L 27/1259 (2013.01); H01L 28/20 (2013.01); H01L 29/66742 (2013.01); H03K 19/00 (2013.01); H01L 23/5223 (2013.01); H01L 23/5227 (2013.01); H01L 23/5283 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A circuit including an inverter is provided for a wiring layer. A semiconductor device is provided with a wiring layer circuit which is formed over an insulating film and includes at least one inverter element. The inverter is provided with a first transistor element and a resistance element which is connected to the first transistor via a connection node. The first transistor element is provided with a gate electrode which is embedded in an interlayer insulating film including the insulating film, a gate insulating film which is formed over the interlayer insulating film and the gate electrode, and a first semiconductor layer which is formed over the gate insulating film between a source electrode and a drain electrode. The resistance element is provided with a second semiconductor layer which functions as a resistance. The first semiconductor layer and the second semiconductor layer are formed in the same layer.

Find Patent Forward Citations

Loading…