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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9368403 B1

PDFFull Text
Date of Patent:
Jun. 14, 2016

Filed:

Mar. 25, 2015

Method for manufacturing a semiconductor device

Applicant:

Renesas Electronics Corporation, Kanagawa, JP;

Inventors:

Hiroshi Sunamura, Kanagawa, JP;

Naoya Inoue, Kanagawa, JP;

Kishou Kaneko, Kanagawa, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Kanagawa, JP;

Attorney:

Young & Thompson

Primary Examiner:

Moazzam Hossain

Int. Cl.
CPC ...
H01L 21/20 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/40 (2006.01); H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 27/06 (2006.01); H01L 23/498 (2006.01); H01L 27/108 (2006.01); H01L 27/11 (2006.01); H01L 27/115 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76895 (2013.01); H01L 27/0688 (2013.01); H01L 27/124 (2013.01); H01L 27/1225 (2013.01); H01L 29/401 (2013.01); H01L 29/66742 (2013.01); H01L 29/78 (2013.01); H01L 29/7869 (2013.01); H01L 29/78642 (2013.01); H01L 21/76849 (2013.01); H01L 21/823885 (2013.01); H01L 23/49822 (2013.01); H01L 27/10858 (2013.01); H01L 27/1104 (2013.01); H01L 27/11551 (2013.01); H01L 2924/0002 (2013.01);
Abstract

The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire.

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