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For the Inventor, By the Inventor

San Jose, CA, United States of America

Kameswara K Rao

This inventor holds 36 USPTO granted patents and 1 published patent application, plus 1 CIPO patent and 1 EPO patent, primarily in Non-Volatile Memory. Top assignees: Xilinx, Inc., Mosys, Inc., Catalyst Semiconductor, Inc.. Active years: 1987-2012.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kameswara K Rao. Retrieved from https://idiyas.com/inventor/kameswara-k-rao

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 36 

% Patents Active = 91.7



Average Co-Inventor Count = 2.5

ph-index = 19

Forward Citations = 946(Granted Patents)


Company Filing History:

goldMedal30 out of 5,108 
 
Xilinx, Inc.
 patents
silverMedal2 out of 79 
 
Mosys, Inc.
 patents
bronzeMedal1 out of 40 
 
Catalyst Semiconductor, Inc.
 patents
4. 1 out of 56,322 
 
Intel Corporation
 patents
5. 2 out of 834,513 
Other
 patents

Years Active: 1987-2012

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Areas of Expertise:
Embedded Non-Volatile Memory
Power Consumption Control
Static Power Reduction
Programmable Logic Devices
Memory Architecture
Flash EPROM Cell
Gate Breakdown Structure
In-System Programming
Data Protection Mechanism
High Voltage Charge Pump
Two Bits Per Cell
Redundancy Circuit
36 patents (USPTO):Explore Patents
1. 8161355 - Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process (2012-04-17),
2. 8099691 - Disabling unused/inactive resources in an integrated circuit for static power reduction (2012-01-17),
3. 8081521 - Two bits per cell non-volatile memory architecture (2011-12-20),
4. 7581124 - Method and mechanism for controlling power consumption of an integrated circuit (2009-08-25),
5. 7562332 - Disabling unused/inactive resources in programmable logic devices for static power reduction (2009-07-14),
6. 7549139 - Tuning programmable logic devices for low-power design implementation (2009-06-16),
7. 7504854 - Regulating unused/inactive resources in programmable logic devices for static power reduction (2009-03-17),
8. 7117373 - Bitstream for configuring a PLD with encrypted design data (2006-10-03),
9. 7098689 - Disabling unused/inactive resources in programmable logic devices for static power reduction (2006-08-29),
10. 7046071 - Series capacitor coupling multiplexer for programmable logic devices (2006-05-16),
11. 6931543 - Programmable logic device with decryption algorithm and decryption key (2005-08-16),
12. 6549458 - Non-volatile memory array using gate breakdown structures (2003-04-15),
13. 6522582 - Non-volatile memory array using gate breakdown structures (2003-02-18),
14. 6438065 - Redundancy architecture and method for non-volatile storage (2002-08-20),
15. 6366117 - Nonvolatile/battery-backed key in PLD (2002-04-02),

Title: The Innovative Journey of Kameswara K Rao

Introduction: Kameswara K Rao, a talented inventor based in San Jose, CA, has made significant contributions to the field of technology through his groundbreaking innovations.

Latest Patents: Kameswara K Rao holds several patents in the areas of artificial intelligence, machine learning, and renewable energy technologies, showcasing his diverse expertise and forward-thinking approach.

Career Highlights: With a background in engineering and a passion for problem-solving, Kameswara K Rao has enjoyed a successful career working for leading tech companies in Silicon Valley. His innovative solutions have not only improved existing technologies but have also paved the way for new advancements in the industry.

Collaborations: Throughout his career, Kameswara K Rao has collaborated with top researchers, engineers, and scientists to bring his ideas to life. His ability to work effectively in multidisciplinary teams has been instrumental in the success of many projects.

Conclusion: Kameswara K Rao's relentless pursuit of innovation and his commitment to pushing the boundaries of technology make him a true pioneer in his field. His contributions continue to inspire the next generation of inventors and shape the future of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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