The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 2009
Filed:
Aug. 11, 2006
Tim Tuan, San Jose, CA (US);
Kameswara K. Rao, San Jose, CA (US);
Robert O. Conn, Laupahoehoe, HI (US);
Tim Tuan, San Jose, CA (US);
Kameswara K. Rao, San Jose, CA (US);
Robert O. Conn, Laupahoehoe, HI (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method of operating a programmable logic device, including the steps of enabling resources of the programmable logic device being used in a circuit design implemented by the programmable logic device, and disabling unused or inactive resources of the programmable logic device that are not being used in the circuit design. The step of disabling can include de-coupling the unused or inactive resources from one or more power supply terminals. Alternatively, the step of disabling can include regulating a supply voltage applied to the unused or inactive resources. The step of disabling can be performed in response to configuration data bits stored by the programmable logic device and/or in response to user controlled signals. The step of disabling can be initiated during design time and/or run time of the programmable logic device.