The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2012

Filed:

Jun. 24, 2009
Applicants:

Tim Tuan, San Jose, CA (US);

Kameswara K. Rao, San Jose, CA (US);

Robert O. Conn, Hakalau, HI (US);

Inventors:

Tim Tuan, San Jose, CA (US);

Kameswara K. Rao, San Jose, CA (US);

Robert O. Conn, Hakalau, HI (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of operating an integrated circuit ('IC') is disclosed. The method includes identifying one or more unused or inactive resources of the IC which will not be used in a circuit design or which are inactive during operation of the IC. The method also includes enabling resources of the IC which will be used in the circuit design, and also disabling one or more unused or inactive resources of the IC from one or more power supply terminals in response to configuration values which are stored in memory cells.


Find Patent Forward Citations

Tuan, Tim. (2012). Disabling unused/inactive resources in an integrated circuit for static power reduction (U.S. Patent No. 8099691). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8099691

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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