The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2009
Filed:
Feb. 20, 2004
Tim Tuan, San Jose, CA (US);
Jan L. Dejong, Cupertino, CA (US);
Kameswara K. Rao, San Jose, CA (US);
Robert O. Conn, Los Gatos, CA (US);
Tim Tuan, San Jose, CA (US);
Jan L. deJong, Cupertino, CA (US);
Kameswara K. Rao, San Jose, CA (US);
Robert O. Conn, Los Gatos, CA (US);
XILINX, Inc., San Jose, CA (US);
Abstract
A method of operating a programmable logic device includes the steps of using a full Vsupply voltage to operate a first set of active blocks of the programmable logic device, and using a reduced supply voltage (e.g., 0.9 V) to operate a second set of active blocks of the programmable logic device. A timing analysis is performed to determine the maximum available timing slack in each active block. Active blocks having a smaller timing slack are grouped in the first set, and are coupled to receive the full Vsupply voltage. Active blocks having a larger timing slack are grouped in the second set, and are coupled to receive the reduced Vsupply voltage. As a result, the active blocks in the second set exhibit reduced power consumption, without adversely affecting the overall speed of the programmable logic device.