The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2009
Filed:
Feb. 20, 2004
Kevin T. Look, Fremont, CA (US);
Michael J. Hart, Palo Alto, CA (US);
Tim Tuan, San Jose, CA (US);
Kameswara K. Rao, San Jose, CA (US);
Robert O. Conn, Los Gatos, CA (US);
Kevin T. Look, Fremont, CA (US);
Michael J. Hart, Palo Alto, CA (US);
Tim Tuan, San Jose, CA (US);
Kameswara K. Rao, San Jose, CA (US);
Robert O. Conn, Los Gatos, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method of operating a programmable logic device, including the steps of using a full Vsupply voltage to operate one or more active blocks of the programmable logic device, and using a reduced supply voltage (e.g., ½ V) to operate one or more inactive blocks of the programmable logic device. The full VDD supply voltage and reduced supply voltage can be provided to the blocks of the programmable logic device through high-voltage n-channel transistors. A boosted voltage, greater than VDD, is applied to the gate of an n-channel transistor to provide the full VDD supply voltage to an active block. A standby voltage, less than VDD, is applied to the gate of an n-channel transistor to provide the reduced supply voltage to an inactive block. The inactive blocks can be determined during run time and/or design time of the programmable logic device.