Jung-dal Choi

This inventor holds 28 USPTO granted patents and 6 published patent applications, primarily in Semiconductor Devices. Top assignee: Samsung Electronics Co., Ltd.. Active years: 1997-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jung-dal Choi. Retrieved from https://idiyas.com/inventor/jung-dal-choi-o7ieetkr

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 28 (Patent Applications = 6)

% Patents Active = 92.9

Average Co-Inventor Count = 2.9

ph-index = 8

Forward Citations = 271(Granted Patents)

Location History:

Kyungki-do, KR (1997 - 2001)
Suwon, KR (2001)
Seongnam-si, KR (2014)
Hwaseong-si, KR (2013 - 2017)

Company Filing History:

28 out of 138,671

Samsung Electronics Co., Ltd.

patents

Years Active: 1997-2017

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Areas of Expertise:

FinFET

Resistive Memory

Non-Volatile Memory

Semiconductor Fabrication

Conductive Line Structures

Vertical Memory Devices

Flash Memory

Integrated Circuits

Quantum-Dot Storage

Memory Cell Transistors

Programming Methods

Strain-Relaxed Buffer Layer

28 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9564435 - Semiconductor device including FinFETs having different gate structures and method of manufacturing the semiconductor device (2017-02-07),

2. 9450049 - Semiconductor device and method for fabricating the same (2016-09-20),

3. 9450025 - Resistive memory device and method of operating resistive memory device (2016-09-20),

4. 9425198 - Semiconductor device having strain-relaxed buffer layer and method of manufacturing the same (2016-08-23),

5. 9391269 - Variable resistance memory devices (2016-07-12),

6. 9391134 - Fin field effect transistor, semiconductor device including the same and method of forming the semiconductor device (2016-07-12),

7. 9373664 - Variable resistance memory devices and methods of manufacturing the same (2016-06-21),

8. 9349879 - Non-volatile memory devices including blocking insulation patterns with sub-layers having different energy band gaps (2016-05-24),

9. 9318419 - Conductive line structures and methods of forming the same (2016-04-19),

10. 9202932 - Semiconductor devices and methods of manufacturing the same (2015-12-01),

11. 9159432 - Method of programming a nonvolatile memory device (2015-10-13),

12. 9111619 - Semiconductor memory devices and methods of manufacturing the same (2015-08-18),

13. 8969947 - Vertical memory devices with quantum-dot charge storage cells (2015-03-03),

14. 8907398 - Gate structure in non-volatile memory device (2014-12-09),

15. 8884377 - Conductive line structures and methods of forming the same (2014-11-11),

Title: Jung-dal Choi: Pioneering Inventor from Hwaseong-si, KR

Introduction: Jung-dal Choi is a distinguished inventor hailing from Hwaseong-si, South Korea, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Jung-dal Choi holds several patents in the realm of electronics and telecommunications, showcasing his expertise and innovative mindset in developing cutting-edge solutions for modern challenges.

Career Highlights: With a career spanning over two decades, Jung-dal Choi has worked tirelessly to push the boundaries of technological advancements, with a focus on creating solutions that enhance efficiency and connectivity in various industries.

Collaborations: Throughout his career, Jung-dal Choi has collaborated with leading tech companies and research institutions to further his inventions and bring them to market, solidifying his reputation as a visionary in the field.

Conclusion: Jung-dal Choi's relentless pursuit of innovation and his passion for creating impactful solutions have cemented his legacy as a pioneering inventor in Hwaseong-si, South Korea, inspiring future generations to push the boundaries of what is possible in the world of technology.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

6 patents pending: