The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2014

Filed:

Feb. 11, 2014
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventors:

Jang-Gn Yun, Hwaseong-si, KR;

Jung-Dal Choi, Hwaseong-si, KR;

Kwang-Soo Seol, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 27/115 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7926 (2013.01); H01L 29/66833 (2013.01); H01L 21/28282 (2013.01); H01L 27/1157 (2013.01); H01L 29/792 (2013.01); H01L 27/11582 (2013.01);
Abstract

A gate structure of a non-volatile memory device and a method of forming the same including a tunnel oxide layer pattern, a charge trap layer pattern, a blocking dielectric layer pattern having the uppermost layer including a material having a first dielectric constant greater than that of a material included in the tunnel oxide layer pattern, and first and second conductive layer patterns. The gate structure includes a first spacer to cover at least the sidewall of the second conductive layer pattern. The gate structure includes a second spacer covering the sidewall of the first spacer and the sidewall of the first conductive layer pattern and including a material having a second dielectric constant equal to or greater than the first dielectric constant. In the non-volatile memory device including the gate structure, erase saturation caused by back tunneling is reduced.


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