The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2016

Filed:

Jun. 11, 2015
Applicants:

Seung-jae Jung, Gyeonggi-Do, KR;

Youn-seon Kang, Yongin-Si, KR;

Jung-dal Choi, Hwaseong-Si, KR;

Inventors:

Seung-Jae Jung, Gyeonggi-Do, KR;

Youn-Seon Kang, Yongin-Si, KR;

Jung-Dal Choi, Hwaseong-Si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 45/00 (2006.01); H01L 27/22 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2463 (2013.01); H01L 27/224 (2013.01); H01L 27/2409 (2013.01); H01L 27/2418 (2013.01); H01L 27/2481 (2013.01); H01L 45/04 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); H01L 45/144 (2013.01); H01L 45/146 (2013.01); H01L 45/1675 (2013.01);
Abstract

A resistive memory device includes a plurality of memory cell pillars arranged in a line in one direction and each having a memory layer and a top electrode layer connected to the memory layer, a top conductive line having a plurality of protrusions extending downwardly and between which pockets in the bottom of the top conductive line are defined, and a plurality of insulating pillars. The protrusions of the top conductive line face and are electrically connected to the memory cell pillars, respectively, so as to be electrically connected to the memory layer through the top electrode layer of the memory cell pillar. The insulating pillars extend from insulating spaces, between side wall surfaces of the memory layers and top electrode layers of the memory cell pillars, into the pockets in the bottom of the top conductive line.


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