The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2017
Filed:
Jun. 29, 2015
Eun-ae Chung, Hwaseong-si, KR;
Jung-dal Choi, Hwaseong-si, KR;
Toshiro Nakanishi, Seongnam-si, KR;
Yu-bin Kim, Suwon-si, KR;
Gab-jin Nam, Seoul, KR;
Dong-kyu Lee, Suwon-si, KR;
Guangfan Jiao, Suwon-si, KR;
Eun-ae Chung, Hwaseong-si, KR;
Jung-dal Choi, Hwaseong-si, KR;
Toshiro Nakanishi, Seongnam-si, KR;
Yu-bin Kim, Suwon-si, KR;
Gab-jin Nam, Seoul, KR;
Dong-kyu Lee, Suwon-si, KR;
Guangfan Jiao, Suwon-si, KR;
Abstract
A semiconductor device includes a substrate having a logic device region including logic devices thereon, and an input/output (I/O) device region including I/O devices thereon adjacent the logic device region. A first fin field-effect transistor (FinFET) on the logic device region includes a first semiconductor fin protruding from the substrate, and a triple-gate structure having a first gate dielectric layer and a first gate electrode thereon. A second FinFET on the I/O device region includes a second semiconductor fin protruding from the substrate, and a double-gate structure having a second gate dielectric layer and a second gate electrode thereon. The first and second gate dielectric layers have different thicknesses. Related devices and fabrication methods are also discussed.