Owego, NY, United States of America

Joseph Michael Swenton

This inventor holds 20 USPTO granted patents, primarily in IC Test Diagnostics. Top assignees: Cadence Design Systems, Inc., International Business Machines Corporation, Other. Active years: 1996-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Joseph Michael Swenton. Retrieved from https://idiyas.com/inventor/joseph-michael-swenton

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 80.0

Average Co-Inventor Count = 3.4

ph-index = 5

Forward Citations = 74(Granted Patents)


Location History:

  • Endicott, NY (US) (2014)
  • Owego, NY (US) (1996 - 2024)

Company Filing History:


Years Active: 1996-2024

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Areas of Expertise:
ATPG Test Patterns
Fault Identification
Electronic Circuit Analysis
Defect Diagnosis
Scan Chain Diagnosis
Test Vector Generation
Statistical Volume Diagnosis
Hierarchical Design
Analog Fault Visualization
Failure Locations
Cell-Aware Defects
SDF Testing
20 patents (USPTO):Explore Patents

Title: Joseph Michael Swenton: Innovator in Integrated Circuit Testing

Introduction

Joseph Michael Swenton, hailing from Owego, NY, is a prominent inventor known for his significant contributions to the field of integrated circuit (IC) testing. With an impressive portfolio of 20 patents, Swenton has made remarkable advancements in diagnosing faults and defects in IC designs.

Latest Patents

Among Swenton's latest innovations are two notable patents focused on enhancing IC testing methodologies. The first patent, titled "Utilizing transition ATPG test patterns to detect multicycle faults and/or defects in an IC chip," describes an IC test engine that generates two-cycle delay test patterns. These patterns target multicycle faults in IC chips by employing a scan-in shift window and a capture window at differing clock frequencies. This innovative approach enables effective fault simulation against specific defects within the IC design.

The second patent, "Diagnosing multicycle transition faults and/or defects with AT-speed ATPG test patterns," presents a further development in IC testing. This patent involves generating N-cycle at-speed test patterns that assess candidate faults in IC designs. It includes a diagnostics engine that processes test result data to identify discrepancies between expected results and actual measurements, ultimately utilizing fault simulation to diagnose multicycle transition faults.

Career Highlights

Joseph Michael Swenton has an extensive career that includes notable tenures at leading technology firms. He has worked at Cadence Design Systems, Inc., where he contributed to advancements in electronic design automation, and at IBM, a pioneer in the technology industry. His work in these organizations has paved the way for innovative IC testing solutions that address critical industry challenges.

Collaborations

Throughout his career, Swenton has collaborated with esteemed professionals in the field, including his coworkers Thomas Webster Bartenstein and Arvind Chokhani. Their collective expertise has fostered an environment of innovation, enabling the development of groundbreaking IC testing technologies.

Conclusion

Joseph Michael Swenton stands out as a leading inventor in the realm of integrated circuit testing, with a wealth of patents that underline his dedication to resolving complex technical challenges. His contributions have had a lasting impact on the industry, ensuring that the reliability of electronic components continues to meet the growing demands of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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