System and method for diagnosing failure locations in electronic circuits

Abstract

Embodiments for diagnosing failure locations in one or more electronic circuits. Embodiments may include generating a plurality of core instances of at least one core, for each electronic circuit, with one or more outputs and compressing the outputs of each instance into primary output pins based upon compression equations. Embodiments may include applying test patterns to the plurality of core instances and identifying failures based upon compressed test patterns received at the primary output pins. Embodiments may include performing fault selection on a single core instance for each failure associated with the plurality of core instances and performing fault simulations on the single core instance for each candidate faults associated with the plurality of core instances. Embodiments may include generating fault signatures for each detected fault based upon the instances associated with each detected fault and analyzing each fault signature to determine failure locations.