Company Filing History:

11 out of 2,548

Cadence Design Systems, Inc.

patents

8 out of 164,244

International Business Machines Corporation

patents

where one patent can have more than one assignee

Years Active: 1996-2018

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18 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9864004 - System and method for diagnosing failure locations in electronic circuits (2018-01-09),

2. 9404969 - Method and apparatus for efficient hierarchical chip testing and diagnostics with support for partially bad dies (2016-08-02),

3. 8887019 - Method and system for providing efficient on-product clock generation for domains compatible with compression (2014-11-11),

4. 8732632 - Method and apparatus for automated extraction of a design for test boundary model from embedded IP cores for hierarchical and three-dimensional interconnect test (2014-05-20),

5. 8468404 - Method and system for reducing switching activity during scan-load operations (2013-06-18),

6. 8296703 - Fault modeling for state retention logic (2012-10-23),

7. 7693676 - Low power scan test for integrated circuits (2010-04-06),

8. 7523370 - Channel masking during integrated circuit testing (2009-04-21),

9. 7487420 - System and method for performing logic failure diagnosis using multiple input signature register output streams (2009-02-03),

10. 7435990 - Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer (2008-10-14),

11. 7381986 - Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer (2008-06-03),

12. 7103816 - Method and system for reducing test data volume in the testing of logic products (2006-09-05),

13. 6986090 - Method for reducing switching activity during a scan operation with limited impact on the test coverage of an integrated circuit (2006-01-10),

14. 6804803 - Method for testing integrated logic circuits (2004-10-12),

15. 6782501 - System for reducing test data volume in the testing of logic products (2004-08-24),

Title: Brion L Keller: Innovator in Electronic Circuit Diagnostics

Introduction

Brion L Keller is a notable inventor based in Binghamton, NY (US), recognized for his contributions to the field of electronic circuit diagnostics. With a total of 18 patents to his name, Keller has made significant advancements in methods and systems that enhance the reliability and efficiency of electronic circuits.

Latest Patents

Keller's latest patents include a "System and method for diagnosing failure locations in electronic circuits." This invention focuses on diagnosing failure locations in one or more electronic circuits by generating multiple core instances and applying test patterns to identify failures. Another significant patent is the "Method and apparatus for efficient hierarchical chip testing and diagnostics with support for partially bad dies." This invention addresses the challenges of testing multiple instances of identical cores in a chip, allowing for efficient identification of defective cores during testing.

Career Highlights

Throughout his career, Brion L Keller has worked with prominent companies such as Cadence Design Systems, Inc. and IBM. His experience in these organizations has contributed to his expertise in electronic design automation and circuit diagnostics.

Collaborations

Keller has collaborated with notable professionals in the field, including Donald Lawrence Wheater and Bernd K Koenemann. These collaborations have further enriched his work and innovations in electronic circuit diagnostics.

Conclusion

Brion L Keller's contributions to electronic circuit diagnostics through his innovative patents and collaborations highlight his significant role in advancing technology in this field. His work continues to influence the design and testing of electronic circuits, ensuring greater reliability and efficiency.

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