The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 23, 2012
Filed:
Dec. 19, 2008
Krishna Chakravadhanula, Vestal, NY (US);
Steven L. Gregor, Owego, NY (US);
Brion L. Keller, Binghamton, NY (US);
Vivek Chickermane, Ithaca, NY (US);
Krishna Chakravadhanula, Vestal, NY (US);
Steven L. Gregor, Owego, NY (US);
Brion L. Keller, Binghamton, NY (US);
Vivek Chickermane, Ithaca, NY (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method for modeling state-retention logic includes: specifying a circuit that includes an arrangement of circuit elements, wherein a portion of the circuit is organized into a power domain with a power-domain control for effecting power variations within the power domain, and the power domain includes a state-retention cell that includes a retention element with a retention-element control for saving state-retention-cell values in the retention element during power variations in the power domain; determining one or more pattern faults for detecting defects in state-retention operation of the circuit by associating circuit element values with values for the power-domain control or the retention-element control; and saving one or more values for the one or more pattern faults.