The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2006
Filed:
Jan. 23, 2001
Frank O. Distler, Williston, VT (US);
Leonard O. Farnsworth, Iii, Lincoln, VT (US);
Andrew Ferko, Waterbury, VT (US);
Brion L. Keller, Conklin, NY (US);
Bernd K. Koenemann, San Jose, CA (US);
Donald L. Wheater, Hinesburg, VT (US);
Frank O. Distler, Williston, VT (US);
Leonard O. Farnsworth, III, Lincoln, VT (US);
Andrew Ferko, Waterbury, VT (US);
Brion L. Keller, Conklin, NY (US);
Bernd K. Koenemann, San Jose, CA (US);
Donald L. Wheater, Hinesburg, VT (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method and system for reducing test data volume in the testing of logic products such as integrated circuit chips. Test data loaded by a tester into the logic product to apply to portions of combinational logic circuitry therein in order to detect faults comprises 'care' bits and 'non-care' bits. The care bits target focal faults of interest in the logic circuitry being tested while the non-care bits do not. According to the invention, non-care bits in the test vector data are filled with repetitive background data to provide for a high degree of compressibility of the test vector data. A substantial portion of the care bits may also be set to a repetitive value and the original values later recovered.