The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2019
Filed:
Jul. 20, 2016
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Sameer Chakravarthy Chillarige, Greater Noida, IN;
Anil Malik, New Delhi, IN;
Sharjinder Singh, Delhi, IN;
Joseph Michael Swenton, Owego, NY (US);
Assignee:
CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3183 (2006.01); G01R 31/3181 (2006.01); G01R 31/3185 (2006.01); G01R 31/317 (2006.01); G01R 31/3177 (2006.01); G01R 31/3193 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318307 (2013.01); G01R 31/31813 (2013.01); G01R 31/31835 (2013.01); G01R 31/318314 (2013.01); G01R 31/318357 (2013.01); G01R 31/318547 (2013.01); G01R 31/318569 (2013.01); G01R 31/317 (2013.01); G01R 31/3177 (2013.01); G01R 31/3193 (2013.01);
Abstract
A method for defect identification for an integrated circuit includes determining a defect ranking technique, applying at least two defect identification techniques and generating a defect report corresponding to each technique, comparing the defect reports and generating probable defect locations, prioritizing the probable defect locations according to the defect ranking technique; and generating a report of the prioritized probable defect locations.