The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2023

Filed:

Jul. 02, 2021
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Arvind Chokhani, Murphy, TX (US);

Joseph Michael Swenton, Owego, NY (US);

Martin Thomas Amodeo, Santa Clara, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3177 (2006.01); G06F 30/392 (2020.01); G06F 30/31 (2020.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G06F 30/392 (2020.01); G06F 30/31 (2020.01);
Abstract

An integrated circuit (IC) test engine generates single cycle test patterns for testing for candidate faults and/or defects of a first set of static faults and/or defects of an IC design. A diagnostics engine receives single cycle test result data characterizing application of the single cycle test patterns to a fabricated IC chip based on the IC design and fault-simulates a subset of the single cycle test patterns against a fault model that includes multicycle faults and/or defects utilizing sim-shifting to diagnose a second set of static faults and/or defects in the fabricated IC chip that are only detectable with multicycle test patterns. The diagnostics engine further scores candidate faults and/or defects in the first set of static faults and/or defects and the second set of static faults and/or defects for applicable test patterns to determine a most likely fault and/or defect present in the fabricated IC chip.


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