Cadence Design Systems, Inc.

International Business Machines Corporation

Other

Joseph Michael Swenton

Thomas Webster Bartenstein

Arvind Chokhani

Sameer Chakravarthy Chillarige

Sharjinder Singh

Anil Malik

Martin Thomas Amodeo

David Sliwinski

Santosh Subhaschandra Malagi

Richard Schoonover

Donald John O'Riordan

Brion L Keller

Richard Frank Rizzolo

Bryan J Robbins

Patrick Gallagher

Shaleen Bhabu

Robert M Mesnard

Gilbert C Vandling

Kevin William McCauley

Hao Ji

Sonam Kathpalia

Richard Gabrielson

William B Maloney

Sameer H Chakravarthy

Ratan Deep H Singh

Robert Jordan Asher

An integrated circuit (IC) test engine generates N-cycle at-speed test patterns for testing for candidate faults and/or defects of a first set of transition faults and/or defects of an IC design. A diagnostics engine that receives test result data characterizing application of the N-cycle at-speed test patterns to a fabricated IC chip based on the IC design by an ATE, in which the test result data includes a set of miscompare values characterizing a difference between an expected result and a result measured by the ATE for a given N-cycle at-speed test pattern. The diagnostics engine employs a fault simulator to fault-simulate the N-cycle at-speed test patterns against a fault model that includes a first set of transition faults and/or defects and fault-simulate a subset of the N-cycle at-speed test patterns against a fault model that includes multicycle transition faults and/or defects utilizing sim-shifting.

Diagnosing multicycle transition faults and/or defects with AT-speed ATPG test patterns

An IC test engine generates a plurality of two-cycle delay test patterns that target a first set of multicycle faults and/or defects of a fabricated IC chip based on an IC design. Each two-cycle delay test pattern includes a scan-in shift window operating at a test clock frequency, and a capture window with a launch cycle and a capture cycle operating at a functional clock frequency. The IC test engine fault simulates the plurality of two-cycle delay test patterns against a second set of multicycle faults and/or defects in the IC design utilizing sim-shifting, such that a state of the IC design after at least a last two shift clock cycles of a scan-in shift in window of each two-cycle delay test pattern of the plurality of two-cycle delay test patterns are fault simulated to provide two fault initialization cycles for detection of a multicycle delay fault and/or defect.

Utilizing transition ATPG test patterns to detect multicycle faults and/or defects in an IC chip

An integrated circuit (IC) test engine generates single cycle test patterns for testing for candidate faults and/or defects of a first set of static faults and/or defects of an IC design. A diagnostics engine receives single cycle test result data characterizing application of the single cycle test patterns to a fabricated IC chip based on the IC design and fault-simulates a subset of the single cycle test patterns against a fault model that includes multicycle faults and/or defects utilizing sim-shifting to diagnose a second set of static faults and/or defects in the fabricated IC chip that are only detectable with multicycle test patterns. The diagnostics engine further scores candidate faults and/or defects in the first set of static faults and/or defects and the second set of static faults and/or defects for applicable test patterns to determine a most likely fault and/or defect present in the fabricated IC chip.

Diagnosing multicycle faults and/or defects with single cycle ATPG test patterns

An integrated circuit (IC) test engine can generate a plurality of single cycle test patterns that target a plurality of static single cycle defects of a fabricated IC chip based on an IC design. The IC test engine can also fault simulate the plurality of single cycle test patterns against a plurality of multicycle defects in the IC design, wherein a given single cycle test pattern of the plurality of single cycle test patterns is sim-shifted to enable detection of a given multicycle fault and/or defect of the plurality of multicycle faults and/or defects.

Utilizing single cycle ATPG test patterns to detect multicycle cell-aware defects

A fault rules engine generates a plurality of fault rules files, each of the fault rules files is associated with a respective cell type of a plurality of cell types in an integrated circuit (IC) design. Each fault rules file includes data quantifying a nominal delay for a given two-cycle test pattern and data quantifying a delta delay for the given two-cycle test pattern corresponding to a given candidate defect of a plurality of candidate defects of a given cell type of the plurality of cell types in the IC design. An IC test engine extracts an input to output propagation delay for each cell instance from a standard delay format (SDF) file for the IC design and generates cell-aware test patterns for each cell instance of each cell type in the IC design based on the plurality of fault rules files and the extracted input to output propagation delays.

Timed transition cell-aware ATPG using fault rule files and SDF for testing an IC chip

A fault rules engine generates a plurality of fault rules files. Each of the fault rules files is associated with a respective cell type of a plurality of cell types in an integrated circuit (IC) design, and each fault rules file of the plurality of fault rules files can include data quantifying a nominal delay for a given two-cycle test pattern of a set of two-cycle test patterns and data quantifying a delta delay for the given two-cycle test pattern corresponding to a given candidate defect of a plurality of candidate defects for a given cell type in the IC design. An IC test engine generates cell-aware test patterns based on the plurality of fault rules files to test a fabricated IC chip that is based on the IC design for defects corresponding to a subset of the plurality of candidate defects characterized in the plurality of fault rules files.

Fault rules files for testing an IC chip

A method for defect identification for an integrated circuit includes determining a defect ranking technique, applying at least two defect identification techniques and generating a defect report corresponding to each technique, comparing the defect reports and generating probable defect locations, prioritizing the probable defect locations according to the defect ranking technique; and generating a report of the prioritized probable defect locations.

Highly accurate defect identification and prioritization of fault locations

The present disclosure relates to a system and method for performing scan chain diagnosis of an electronic design. The method may include identifying, at a computing device, at least one failing scan chain associated with the electronic design. The method may also include selecting a plurality of defect locations associated with the at least one failing scan chain, wherein the plurality of defect locations corresponds to a number of parallel patterns that a simulator is configured to process. The method may further include selecting a sliced failing pattern set and generating a plurality of copies of a pattern associated with the sliced failing pattern set, wherein each of the plurality of copies corresponds to one of the plurality of defect locations. The method may also include simulating the plurality of copies of the pattern in parallel.

System and method performing scan chain diagnosis of an electronic design

Systems and methods disclosed herein provide for automatically diagnosing mis-compares detected during simulation of Automatic Test Pattern Generation ('ATPG') generated test patterns. Embodiments of the systems and methods provide for determining the origin of a mis-compare based on an analysis of the generated test patterns with a structural simulator and a behavioral simulator.

Method and apparatus for automatic diagnosis of mis-compares

Embodiments for diagnosing failure locations in one or more electronic circuits. Embodiments may include generating a plurality of core instances of at least one core, for each electronic circuit, with one or more outputs and compressing the outputs of each instance into primary output pins based upon compression equations. Embodiments may include applying test patterns to the plurality of core instances and identifying failures based upon compressed test patterns received at the primary output pins. Embodiments may include performing fault selection on a single core instance for each failure associated with the plurality of core instances and performing fault simulations on the single core instance for each candidate faults associated with the plurality of core instances. Embodiments may include generating fault signatures for each detected fault based upon the instances associated with each detected fault and analyzing each fault signature to determine failure locations.

System and method for diagnosing failure locations in electronic circuits

In order to detect and locate defects, or faults, in a plurality of chips or other circuits sharing a common design, said chips are each tested for incorrect outputs, or failures, in response to inputs. The incorrect outputs are then collectively diagnosed in a single simulation by simulating a series of suspected fault candidates on a simulated chip of the chip design, and afterward comparing the incorrect outputs generated by each fault candidate to the incorrect outputs of the individual chips, to determine if a fault candidate generates all failures for a chip and no others. The test inputs and expected outputs may be predetermined through Automatic Test Pattern Generation. The fault candidates may be determined by use of a backtrace process such as back cone tracing. The failures may be recorded in association with a measure point, the input pattern that resulted in the failure, and the failure value.

Method and system of collective failure diagnosis for multiple electronic circuits

An apparatus and method for visualizing faults in a circuit design includes simulating faults for a circuit design in a layout and a schematic, editing the layout and schematic to include the simulated fault, and linking the layout and schematic with the fault simulation.

Analog fault visualization system and method for circuit designs

A method and system for subnet defect diagnostics through fault compositing is disclosed. A testing apparatus generates callout data for an integrated circuit device under test. A computer received the callout data, which includes a list of faults. Each fault of the list of faults has associated with it one or more failures and/or conflicts. In order to explain the failures, two or more faults are selected and composited, yielding a composite fault having a composite conflict count. The composite fault is assigned a score based on the composite conflict count, which score determines a candidate composite that best explains the faults of the list of faults. This procedure may be repeated to explain all the failures.

Method and system for subnet defect diagnostics through fault compositing

A method and system for test vector selection in statistical volume diagnosis using failed test data is disclosed. A computer-implemented method receives failures representing defects detected by an integrated circuit testing apparatus from a plurality of integrated circuits. Each of the plurality of integrated circuits is tested with a set of test vectors generated by the integrated circuit testing apparatus, and each of the plurality of failures is associated with a failed test vector. Using a first ranking scheme, each of the failures is given a rank and the corresponding failed test vector in each of the plurality of integrated circuits is annotated with the rank. The annotated failed test vectors are grouped using a grouping scheme, and each of the groups is given a group rank. A first group of failed test vectors is selected based on the group rank and diagnostics is run on the first group of failed test vectors.

Method and system for selecting test vectors in statistical volume diagnosis using failed test data

Systems, methods, and computer readable media storing instructions for such methods relate to generating test vectors that can be used for exercising a particular area of interest in an integrated circuit. The test vectors generally include a non-overlapping repeating and/or predictable sequence of care bits (a care bit pattern) that can be used by a tester to cause the exercise of the area and collect emissions caused by exercising the area. Such emissions can be used for analysis and debugging of the circuit and/or a portion of it. Aspects can include providing a synchronization signal that can be used by a tester to allow sensor activation at appropriate times.

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Owego, NY, United States of America

Joseph Michael Swenton