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For the Inventor, By the Inventor

Pleasant Valley, NY, United States of America

Jin Zheng Wallner

This inventor holds 12 USPTO granted patents and 1 published patent application. Top assignees: Globalfoundries Inc., International Business Machines Corporation, Freescale Semiconductor,inc.. Active years: 2011-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jin Zheng Wallner. Retrieved from https://idiyas.com/inventor/jin-zheng-wallner

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 12 

% Patents Active = 41.7

Average Co-Inventor Count = 3.2

ph-index = 4

Forward Citations = 53(Granted Patents)


Location History:

  • Pleasant Valley, NY (US) (2011 - 2015)
  • Albany, NY (US) (2016 - 2021)

Company Filing History:

goldMedal6 out of 5,671 
 
Globalfoundries Inc.
 patents
silverMedal5 out of 166,325 
 
International Business Machines Corporation
 patents
bronzeMedal1 out of 5,491 
 
Freescale Semiconductor,inc.
 patents
4. 1 out of 1,087 
 
Globalfoundries U.S. Inc.
 patents
5. 1 out of 2,891 
 
Stmicroelectronics Gmbh
 patents
where one patent can have more than one assignee

Years Active: 2011-2021

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12 patents (USPTO):Explore Patents
1. 11056591 - Epitaxial structures of semiconductor devices that are independent of local pattern density (2021-07-06),
2. 10580684 - Self-aligned single diffusion break for fully depleted silicon-on-insulator and method for producing the same (2020-03-03),
3. 9917103 - Diffusion break forming after source/drain forming and related IC structure (2018-03-13),
4. 9899257 - Etch stop liner for contact punch through mitigation in SOI substrate (2018-02-20),
5. 9887135 - Methods for providing variable feature widths in a self-aligned spacer-mask patterning process (2018-02-06),
6. 9418982 - Multi-layered integrated circuit with selective temperature coefficient of resistance (2016-08-16),
7. 9412843 - Method for embedded diamond-shaped stress element (2016-08-09),
8. 9171935 - FinFET formation with late fin reveal (2015-10-27),
9. 8940634 - Overlapping contacts for semiconductor device (2015-01-27),
10. 8787074 - Static random access memory test structure (2014-07-22),
11. 8124534 - Multiple exposure and single etch integration method (2012-02-28),
12. 7883953 - Method for transistor fabrication with optimized performance (2011-02-08),

Title: Inventor Jin Zheng Wallner

Introduction: Jin Zheng Wallner is a prolific inventor based in Pleasant Valley, NY, known for his groundbreaking contributions to various fields.

Latest Patents: Jin Zheng Wallner's most recent patents include innovative designs in renewable energy technologies and advanced medical devices.

Career Highlights: Throughout his career, Jin Zheng Wallner has been recognized for his inventive spirit, receiving multiple awards for his groundbreaking patents and contributions to the scientific community.

Collaborations: Jin Zheng Wallner has collaborated with leading research institutions and universities to further develop his inventions, showcasing his dedication to pushing the boundaries of innovation.

Conclusion: Jin Zheng Wallner's passion for innovation and his relentless pursuit of excellence continue to make him a prominent figure in the world of inventors.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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