The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 08, 2011
Filed:
Sep. 30, 2008
Da Zhang, Hopewell Junction, NY (US);
Voon-yew Thean, Austin, TX (US);
Christopher V. Baiocco, Newburgh, NY (US);
Jie Chen, Singapore, SG;
Weipeng LI, Beacon, NY (US);
Young Way Teh, Singapore, SG;
Jin Wallner, Pleasant Valley, NY (US);
Da Zhang, Hopewell Junction, NY (US);
Voon-Yew Thean, Austin, TX (US);
Christopher V. Baiocco, Newburgh, NY (US);
Jie Chen, Singapore, SG;
Weipeng Li, Beacon, NY (US);
Young Way Teh, Singapore, SG;
Jin Wallner, Pleasant Valley, NY (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A semiconductor process and apparatus includes forming <100> channel orientation CMOS transistors () with enhanced hole mobility in the NMOS channel region and reduced channel defectivity in the PMOS region by depositing a first tensile etch stop layer () over the PMOS and NMOS gate structures, etching the tensile etch stop layer () to form tensile sidewall spacers () on the exposed gate sidewalls, and then depositing a second hydrogen rich compressive or neutral etch stop layer () over the NMOS and PMOS gate structures () and the tensile sidewall spacers (). In other embodiments, a first hydrogen-rich etch stop layer () is deposited and etched to form sidewall spacers () on the exposed gate sidewalls, and then a second tensile etch stop layer () is deposited over the NMOS and PMOS gate structures () and the sidewall spacers ().