The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2018
Filed:
Jan. 04, 2017
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
George R. Mulfinger, Gansevoort, NY (US);
Jin Z. Wallner, Albany, NY (US);
Assignee:
GLOBALFOUNDRIES INC., Grand Cayman, KY (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 21/762 (2006.01); H01L 21/84 (2006.01); H01L 29/417 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/76224 (2013.01); H01L 21/84 (2013.01); H01L 29/0649 (2013.01); H01L 29/401 (2013.01); H01L 29/41783 (2013.01); H01L 29/66545 (2013.01);
Abstract
Methods of forming a diffusion break are disclosed. The method includes forming a diffusion break after source/drain formation, by removing a gate stack of the dummy gate to a buried insulator of an SOI substrate, creating a first opening; and filling the first opening with a dielectric to form the diffusion break. An IC structure includes the diffusion break in contact with an upper surface of the buried insulator. In an optional embodiment, the method may also include simultaneously forming an isolation in an active gate to an STI in the SOI substrate.