The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 2016
Filed:
May. 23, 2014
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Eric C. Harley, Lagrangeville, NY (US);
Judson R. Holt, Wappingers Falls, NY (US);
Jin Z. Wallner, Albany, NY (US);
Thomas A. Wallner, Albany, NY (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/336 (2006.01); H01L 29/66 (2006.01); H01L 21/308 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66636 (2013.01); H01L 21/308 (2013.01); H01L 21/3086 (2013.01); H01L 29/0847 (2013.01); H01L 29/6656 (2013.01); H01L 29/7848 (2013.01); H01L 29/165 (2013.01); H01L 29/66545 (2013.01);
Abstract
A method of manufacturing a semiconductor device with an embedded layer, by anisotropically etching a substrate adjacent to an already formed gate structure. A dummy layer is deposited in the previously etched region, and a second spacer is formed next to the first spacer. The dummy layer is removed, and a second anisotropic etch is performed. A semiconductor substrate is then epitaxially grown in the etched out region to form the embedded layer.