The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2015

Filed:

Mar. 07, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Seong-Dong Kim, LaGrangeville, NY (US);

Myung-Hee Na, Lagrangeville, NY (US);

Jin Z. Wallner, Pleasant Valley, NY (US);

Thomas A. Wallner, Albany, NY (US);

Qintao Zhang, Mount Kisco, NY (US);

Assignee:

GlobalFoundries Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/337 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6681 (2013.01);
Abstract

A FinFET semiconductor device fabrication process includes forming a plurality of FinFET fins upon a semiconductor substrate, forming a first dielectric layer upon the semiconductor substrate so that an upper surface of the first dielectric layer is coplanar with upper surfaces of the FinFET fins, forming a plurality of dummy gates upon the FinFET fins and the first dielectric layer orthogonal to the FinFET fins, revealing the FinFET fins by removing first portions of the first dielectric layer from source-drain regions, removing the dummy gates, and subsequent to the removal of the dummy gates, revealing the FinFET fins by removing second portions of the first dielectric layer from channel regions.


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