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For the Inventor, By the Inventor

Tainan, Taiwan

Jei-Ming Chen

This inventor holds 22 USPTO granted patents and 10 published patent applications, primarily in Semiconductor Technology. Top assignees: United Microelectronics Corp., Taiwan Semiconductor Manufacturing Comp. Ltd., Other. Active years: 2005-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jei-Ming Chen. Retrieved from https://idiyas.com/inventor/jei-ming-chen

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 22 

% Patents Active = 100.0

Average Co-Inventor Count = 4.5

ph-index = 7

Forward Citations = 117(Granted Patents)


Location History:

  • Taipei Hsien, TW (2005 - 2008)
  • Taipei County, TW (2008 - 2009)
  • New Taipei, TW (2016)
  • Tainan, TW (2013 - 2021)

Company Filing History:

goldMedal19 out of 7,278 
 
United Microelectronics Corp.
 patents
silverMedal2 out of 42,872 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents
bronzeMedal1 out of 834,513 
Other
 patents

Years Active: 2005-2025

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Areas of Expertise:
Semiconductor Device
CMOS Transistor
FinFET Structure
Interlevel Dielectric
Strained-Silicon
Metal Oxide Transistor
Interconnect Structure
Damascene Process
Non-Uniform Stress Layer
Isolation Structure
Shallow Trench Isolation
Spatial Semiconductor Structure
22 patents (USPTO):Explore Patents
1. 12217971 - Method for forming semiconductor device (2025-02-04),
2. 10957585 - Semiconductor device and method of forming the same (2021-03-23),
3. 9502305 - Method for manufacturing CMOS transistor (2016-11-22),
4. 9362358 - Spatial semiconductor structure (2016-06-07),
5. 9343573 - Method of fabrication transistor with non-uniform stress layer with stress concentrated regions (2016-05-17),
6. 9105582 - Spatial semiconductor structure and method of fabricating the same (2015-08-11),
7. 9034759 - Method for forming interlevel dielectric (ILD) layer (2015-05-19),
8. 9034726 - Semiconductor process (2015-05-19),
9. 8951884 - Method for forming a FinFET structure (2015-02-10),
10. 8937369 - Transistor with non-uniform stress layer with stress concentrated regions (2015-01-20),
11. 8927388 - Method of fabricating dielectric layer and shallow trench isolation (2015-01-06),
12. 8772904 - Semiconductor structure and process thereof (2014-07-08),
13. 8709901 - Method of forming an isolation structure (2014-04-29),
14. 8692332 - Strained-silicon transistor and method of making the same (2014-04-08),
15. 8674452 - Semiconductor device with lower metal layer thickness in PMOS region (2014-03-18),

Title: The Innovative Journey of Inventor Jei-Ming Chen

Introduction: Jei-Ming Chen, a talented inventor hailing from Tainan, Taiwan, has made significant contributions to the field of innovations with his groundbreaking ideas and inventions.

Latest Patents: Jei-Ming Chen holds several patents in various technological domains, showcasing his versatility and creativity in inventing new solutions to complex problems.

Career Highlights: Throughout his illustrious career, Jei-Ming Chen has been recognized for his pioneering work in developing cutting-edge technologies that have had a profound impact on industries worldwide. His dedication to innovation and problem-solving has led to the successful implementation of numerous inventions.

Collaborations: Jei-Ming Chen has collaborated with leading research institutions, universities, and companies to further his inventions and bring them to market. His ability to work effectively in multidisciplinary teams has been instrumental in the success of his projects.

Conclusion: Jei-Ming Chen's passion for innovation, coupled with his technical expertise, has established him as a prominent figure in the world of inventors. His relentless pursuit of excellence and commitment to pushing the boundaries of what is possible continue to inspire future generations of inventors and innovators.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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