The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2016

Filed:

Oct. 22, 2013
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Yi-Wei Chen, Tai-Chung Hsien, TW;

Teng-Chun Tsai, Tainan, TW;

Chien-Chung Huang, Taichung, TW;

Jei-Ming Chen, New Taipei, TW;

Tsai-Fu Hsiao, Tainan, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/265 (2006.01); H01L 29/165 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823814 (2013.01); H01L 21/26506 (2013.01); H01L 21/823807 (2013.01); H01L 29/165 (2013.01); H01L 29/66628 (2013.01); H01L 29/7843 (2013.01);
Abstract

A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.


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