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For the Inventor, By the Inventor

Wuppertal, Germany

Irmgard Escher-Poeppel

This inventor holds 42 USPTO granted patents and 5 published patent applications, primarily in Semiconductor Packaging. Top assignees: Infineon Technologies Ag, Intel Mobile Communications Gmbh, Intel Deutschland Gmbh. Active years: 2008-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Irmgard Escher-Poeppel. Retrieved from https://idiyas.com/inventor/irmgard-escher-poeppel

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 42 

% Patents Active = 73.8

Average Co-Inventor Count = 3.1

ph-index = 7

Forward Citations = 160(Granted Patents)


Location History:

  • Deggendorf, DE (2016)
  • Regensburg, DE (2008 - 2021)
  • Duggendorf, DE (2015 - 2023)

Company Filing History:

goldMedal32 out of 15,027 
 
Infineon Technologies Ag
 patents
silverMedal4 out of 511 
 
Intel Mobile Communications Gmbh
 patents
bronzeMedal3 out of 254 
 
Intel Deutschland Gmbh
 patents
4. 2 out of 2,201 
 
Infineon Technologies Austria Ag
 patents
5. 1 out of 56,322 
 
Intel Corporation
 patents

Years Active: 2008-2026

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Areas of Expertise:
Semiconductor Package
Flip-Chip Package
Interconnect
Chip Assemblage
Electronic Device
MEMS Device
Graphene Layer
Sensor Device
Power Semiconductor Module
Stackable Package
Encapsulation
42 patents (USPTO):Explore Patents
1. 12604752 - Semiconductor die package (2026-04-14),
2. 12261146 - Semiconductor package (2025-03-25),
3. 11715719 - Semiconductor package and method of forming a semiconductor package (2023-08-01),
4. 11688713 - Additive manufacturing of a frontside or backside interconnect of a semiconductor die (2023-06-27),
5. 11531056 - Predictive chip-maintenance (2022-12-20),
6. 11393742 - Method for fabricating a semiconductor flip-chip package (2022-07-19),
7. 10957671 - Method for fabricating a semiconductor and semiconductor package (2021-03-23),
8. 10886186 - Semiconductor package system (2021-01-05),
9. 10734352 - Metallic interconnect, a method of manufacturing a metallic interconnect, a semiconductor arrangement and a method of manufacturing a semiconductor arrangement (2020-08-04),
10. 10643971 - Method for fabricating a semiconductor and semiconductor package (2020-05-05),
11. 10573533 - Method of reducing a sheet resistance in an electronic device, and an electronic device (2020-02-25),
12. 10438926 - Method for fabricating a semiconductor and semiconductor package (2019-10-08),
13. 10096584 - Method for producing a power semiconductor module (2018-10-09),
14. 10014275 - Method for producing a chip assemblage (2018-07-03),
15. 9818730 - Semiconductor arrangement, method for producing a number of chip assemblies, method for producing a semiconductor arrangement and method for operating a semiconductor arrangement (2017-11-14),

Title: Inventor Irmgard Escher-Poeppel

Introduction: Irmgard Escher-Poeppel is a pioneering inventor based in Wuppertal, Germany, known for her innovative contributions to various fields.

Latest Patents: Escher-Poeppel holds several patents in the areas of sustainable energy solutions and eco-friendly technologies, showcasing her commitment to environmental conservation.

Career Highlights: With a background in engineering and a passion for sustainability, Escher-Poeppel has led groundbreaking projects that have revolutionized the way we approach renewable energy sources.

Collaborations: Throughout her career, Escher-Poeppel has collaborated with leading research institutions and universities to further develop her inventions and bring them to the market successfully.

Conclusion: Irmgard Escher-Poeppel's dedication to creating sustainable solutions and her innovative spirit make her a prominent figure in the world of inventors, inspiring future generations to think creatively for a better tomorrow.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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