The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 03, 2018

Filed:

Mar. 15, 2017
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Alexander Heinrich, Bad Abbach, DE;

Irmgard Escher-Poeppel, Duggendorf, DE;

Martin Gruber, Schwandorf, DE;

Andreas Munding, Regensburg, DE;

Catharina Wille, Regensburg, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/81 (2013.01); H01L 24/09 (2013.01); H01L 24/16 (2013.01); H01L 24/85 (2013.01); H01L 25/50 (2013.01); H01L 2224/095 (2013.01); H01L 2224/16104 (2013.01); H01L 2224/16112 (2013.01); H01L 2224/16137 (2013.01); H01L 2224/4912 (2013.01);
Abstract

One aspect of the invention relates to a method for producing a chip assemblage. Two or more chip assemblies are produced in each case by cohesively and electrically conductively connecting an electrically conductive first compensation lamina to a first main electrode of a semiconductor chip. A control electrode interconnection structure is arranged in a free space between the chip assemblies. Electrically conductive connections are produced between the control electrode interconnection structure and control electrodes of the semiconductor chips of the individual chip assemblies. The chip assemblies are cohesively connected by means of a dielectric embedding compound.


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