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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12772863 B1

PDFFull Text
Date of Patent:
Oct. 20, 2026

Filed:

Dec. 06, 2021

Leaded semiconductor package formation using lead frame with structured central pad

Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Thorsten Meyer, Regensburg, DE;

Fee Hoon Wendy Wong, Melaka, MY;

Thomas Behrens, Wenzenbach, DE;

Eric Lopez Bonifacio, Melaka, MY;

Chau Fatt Chiang, Melaka, MY;

Irmgard Escher-Poeppel, Duggendorf, DE;

Giovanni Ragasa Garbin, Malacca, MY;

Martin Gruber, Schwandorf, DE;

Tien Shyang Law, Schwandorf, MY;

Mohamad Azian Mohamed Azizi, Malacca, MY;

Si Hao Vincent Yeo, Melaka, MY;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:

Murphy, Bilak & Homiller, PLLC

Primary Examiner:

Yu Chen

Int. Cl.
CPC ...
H10W 70/04 (2026.01); H10W 90/00 (2026.01); H10W 70/40 (2026.01); H10W 74/10 (2026.01);
U.S. Cl.
CPC ...
H10W 70/042 (2026.01); H10W 90/811 (2026.01); H10W 70/481 (2026.01); H10W 74/111 (2026.01);
Abstract

A method includes providing a lead frame with a central metal plate and a plurality of leads extending away from the central metal plate, the central metal plate including an upper surface that includes a first mesa that is elevated from recessed regions, mounting a semiconductor die on the upper surface of central metal plate such that a lower surface of the semiconductor die is at least partially disposed on the first mesa, forming electrical interconnections between terminals of the semiconductor die and the leads, forming an encapsulant body on the central metal plate such that the semiconductor die is encapsulated by the encapsulant body and such that the leads protrude out from edge sides of the encapsulant body, and thinning the central metal plate from a rear surface of the central metal plate so as to isolate the first mesa at a lower surface of the encapsulant body.

Find Patent Forward Citations

Meyer, Thorsten. (2026). Leaded semiconductor package formation using lead frame with structured central pad (U.S. Patent No. 12772863). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12772863

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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