Hiromitsu Mashita

This inventor holds 29 USPTO granted patents and 14 published patent applications, primarily in Semiconductor Manufacturing. Top assignees: Kabushiki Kaisha Toshiba, Toshiba Memory Corporation. Active years: 2010-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hiromitsu Mashita. Retrieved from https://idiyas.com/inventor/hiromitsu-mashita

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 29 (Patent Applications = 14)

% Patents Active = 65.5

Average Co-Inventor Count = 4.6

ph-index = 4

Forward Citations = 54(Granted Patents)

Location History:

Sagamihara, JP (2010)
Kawasaki, JP (2010 - 2013)
Kanagawa-ken, JP (2012 - 2016)
Kanagawa, JP (2012 - 2017)
Yokohama, JP (2010 - 2018)
Tokyo, JP (2020)

Company Filing History:

27 out of 53,262

Kabushiki Kaisha Toshiba

patents

2 out of 2,955

Toshiba Memory Corporation

patents

Years Active: 2010-2020

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Areas of Expertise:

Mask Pattern Correction

Semiconductor Device

Pattern Data Generation

Optical Image Calculation

Integrated Circuit

Lithography Simulation

Memory Device

Pattern Verification

Pitch Multiplication

Mask Layout

Pattern Dimension Calculation

Computer Program Product

29 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 10852648 - Mask pattern correction system, and semiconductor device manufacturing method utilizing said correction system (2020-12-01),

2. 9917049 - Semiconductor device having contacts in drawing area and the contacts connected to word lines extending from element formation area (2018-03-13),

3. 9576100 - Pattern data generation method, pattern verification method, and optical image calculation method (2017-02-21),

4. RE46100 - Method of fabricating semiconductor device and semiconductor device (2016-08-08),

5. 9268208 - Pattern generating method, pattern forming method, and pattern generating program (2016-02-23),

6. 9257367 - Integrated circuit device, method for producing mask layout, and program for producing mask layout (2016-02-09),

7. 9177854 - Method of manufacturing semiconductor device using sidewall films for pitch multiplication in forming interconnects (2015-11-03),

8. 9159726 - Semiconductor memory device and method for manufacturing same (2015-10-13),

9. 8984454 - Pattern data generation method, pattern verification method, and optical image calculation method (2015-03-17),

10. 8617999 - Method of manufacturing semiconductor device and computer readable medium for storing pattern size setting program (2013-12-31),

11. 8617773 - Method of correcting mask pattern, computer program product, and method of manufacturing semiconductor device (2013-12-31),

12. 8443310 - Pattern correcting method, mask forming method, and method of manufacturing semiconductor device (2013-05-14),

13. 8347241 - Pattern generation method, computer-readable recording medium, and semiconductor device manufacturing method (2013-01-01),

14. 8336005 - Pattern dimension calculation method and computer program product (2012-12-18),

15. 8307310 - Pattern generating method, method of manufacturing semiconductor device, computer program product, and pattern-shape-determination-parameter generating method (2012-11-06),

Title: Hiromitsu Mashita: Innovator in Semiconductor Technology

Introduction: Hiromitsu Mashita, based in Kanagawa, Japan, is a prominent inventor recognized for his significant contributions in the field of semiconductor technology. With an impressive portfolio of 29 patents, Mashita has driven advancements that enhance the manufacturing processes of semiconductor devices.

Latest Patents: Among his latest innovations are the "Mask Pattern Correction System" and "Semiconductor Device Manufacturing Method Utilizing Said Correction System." The mask pattern correction system is designed to optimize circuit pattern layouts by analyzing stress and calculating displacement correction values. This innovative approach generates correction maps that refine mask pattern designs, ensuring accuracy in semiconductor manufacturing. Additionally, his semiconductor device patent focuses on interconnects connecting to contact areas from the element formation area, leveraging intricate patterning techniques to improve device performance.

Career Highlights: Hiromitsu Mashita has collaborated with notable firms such as Kabushiki Kaisha Toshiba and Toshiba Memory Corporation, where he applied his expertise to advance semiconductor technologies. His work signifies a dedication to innovation and excellence in the competitive field of electronics manufacturing.

Collaborations: Throughout his career, Mashita has worked alongside esteemed colleagues including Toshiya Kotani and Chikaaki Kodama. Their collective efforts have contributed to groundbreaking developments in semiconductor design and manufacturing.

Conclusion: Hiromitsu Mashita stands out as a leading inventor in the semiconductor industry, with a robust patent portfolio and a commitment to technological advancement. His work continues to influence the future of semiconductor manufacturing, showcasing the importance of innovation in driving industry progress.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

14 patents pending: