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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9917049 B1

PDFFull Text
Date of Patent:
Mar. 13, 2018

Filed:

Aug. 02, 2016

Semiconductor device having contacts in drawing area and the contacts connected to word lines extending from element formation area

Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Fumiharu Nakajima, Yokohama, JP;

Toshiya Kotani, Machida, JP;

Hiromitsu Mashita, Yokohama, JP;

Takafumi Taguchi, Yokohama, JP;

Ryota Aburada, Kawasaki, JP;

Chikaaki Kodama, Yokohama, JP;

Assignee:

Toshiba Memory Corporation, Tokyo, JP;

Attorney:

Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.

Primary Examiner:

Michael Jung

Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/033 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 27/06 (2006.01); H01L 27/11524 (2017.01); H01L 27/11551 (2017.01); H01L 27/1157 (2017.01); H01L 27/11578 (2017.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/0337 (2013.01); H01L 21/0338 (2013.01); H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 21/768 (2013.01); H01L 21/76816 (2013.01); H01L 27/0688 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11551 (2013.01); H01L 27/11578 (2013.01);
Abstract

According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)second sidewall film matching a pattern of a n(where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2)×(λ/NA) or less when an exposure wavelength of an exposure device is λ, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.

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