Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kabushiki Kaisha Tosbhia

Hiromitsu Mashita

Toshiya Kotani

Chikaaki Kodama

Fumiharu Nakajima

Takafumi Taguchi

Ryota Aburada

Taiga Uno

Tadahito Fujisawa

Yasunobu Kai

Hidefumi Mukai

Koji Hashimoto

Toshiki Hisada

Seiro Miyoshi

Ayako Nakano

Katsumi Iyanagi

Masahiro Miyairi

Tetsuaki Matsunawa

Atsushi Maesono

Taiki Kimura

Takuya Futatsuyama

Satoshi Tanaka

Tohru Ozaki

Kenji Shiraishi

Sachiyo Ito

Takashi Obara

Kazuhito Kobayashi

Takashi Nakazawa

Kazuyuki Masukawa

Sachiko Kobayashi

Yoshihiro Yanai

Takaki Hashimoto

Takayuki Toba

Yukiyasu Arisawa

Osamu Yamane

Ryuji Ogawa

Hirotaka Ichikawa

Masaki Satake

Kazuo Hatakeyama

Yuko Kono

Minoru Inomoto

Hiroshi Yoshimura

Michiya Takimoto

Yuto Takeuchi

Masanari Kajiwara

Motohiro Okada

Shinichirou Ooki

Kazuyuki Hino

Shuhei Sota

According to one embodiment, a mask pattern correction system includes the following configuration. A stress analysis circuitry divides a layout of a circuit pattern formed using a design mask formed in accordance with mask design data into correction regions, and acquires a displacement amount from the regions. A correction value calculation circuitry calculates a displacement correction value from the displacement amount. A correction map generation circuitry generates a correction map based on a correction value difference of the displacement correction values. A mask position correction circuitry allocates the regions to a layout of the circuit pattern, performs displacement correction of a mask pattern on the design mask by the displacement correction values, and creates a correction mask based on the displacement correction.

Mask pattern correction system, and semiconductor device manufacturing method utilizing said correction system

According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)second sidewall film matching a pattern of a n(where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2)&#xd7;(&#x3bb;/NA) or less when an exposure wavelength of an exposure device is &#x3bb;, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.

Semiconductor device having contacts in drawing area and the contacts connected to word lines extending from element formation area

According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected.

Pattern data generation method, pattern verification method, and optical image calculation method

A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.

Method of fabricating semiconductor device and semiconductor device

One embodiment includes: a step of evaluating an amount of flare occurring through a mask at EUV exposure; a step of providing a dummy mask pattern on the mask based on the evaluated result of the amount of flare; and a step of executing a flare correction and an optical proximity correction on a layout pattern. The layout pattern is provided by the EUV exposure through the mask with the dummy mask pattern.

Pattern generating method, pattern forming method, and pattern generating program

According to one embodiment, a method for producing a mask layout of an exposure mask for forming wiring of an integrated circuit device, includes estimating shape of the wiring formed based on an edge of a pattern included in an initial layout of the exposure mask. The method includes modifying shape of the edge if the estimated shape of the wiring does not satisfy a requirement.

Integrated circuit device, method for producing mask layout, and program for producing mask layout

Method of manufacturing semiconductor device using sidewall films for pitch multiplication in forming interconnects

According to one embodiment, a semiconductor memory device includes a semiconductor substrate and a memory array. The semiconductor substrate has a first face. The memory array region is provided on the first face and includes a plurality of semiconductor pillars. The semiconductor pillars extend in a first direction perpendicular to the first face. Each of the semiconductor pillars includes a plurality of memory cells connected in series. Each of the semiconductor pillars is disposed at the nodes of a honeycomb shape when viewed in the first direction. When the semiconductor pillars are projected onto a first plane along the first and second directions perpendicular to the first direction, a component in the second direction of an interval between the semiconductor pillars has first and second intervals repeated alternately. The second interval is an integer multiple of the first interval greater than or equal to 2.

Semiconductor memory device and method for manufacturing same

In the method of correcting a mask pattern according to the embodiments, a mask pattern correction amount for a reference flare value is calculated as a reference mask correction amount, for every type of patterns within the layout, and a change amount of the mask pattern correction amount corresponding to the change amount of the flare value is calculated as the change amount information. A mask pattern corresponding to the flare value of the pattern is created based on the reference mask correction amount and the change amount information corresponding to the pattern, extracted from the information having the pattern, the reference mask correction amount, and the change amount information correlated with each other, and based on a difference between the flare value of the pattern and the reference flare value.

Method of correcting mask pattern, computer program product, and method of manufacturing semiconductor device

A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps.

Method of manufacturing semiconductor device and computer readable medium for storing pattern size setting program

A pattern correcting method of an embodiment computes a distribution of pattern coverages on a design layout of a circuit pattern in the vicinity of a position that becomes an error pattern in a case where an on-substrate pattern is formed. Then, an area on the design layout in which a difference in the distribution of the pattern coverages becomes small by adding an addition pattern is set as an addition area. Next, addition pattern candidates to be added to the addition area are generated, an addition pattern to be added to the design layout is selected from the candidates on the basis of a predetermined selection criterion, and the addition pattern is added to the addition area.

Pattern correcting method, mask forming method, and method of manufacturing semiconductor device

A pattern generation method includes: acquiring a first design constraint for first patterns to be formed on a process target film by a first process, the first design constraint using, as indices, a pattern width of an arbitrary one of the first patterns, and a space between the arbitrary pattern and a pattern adjacent to the arbitrary pattern; correcting the first design constraint in accordance with pattern conversion by the second process, and thereby acquiring a second design constraint for the second pattern which uses, as indices, two patterns on both sides of a predetermined pattern space of the second pattern; judging whether the design pattern fulfils the second design constraint; and changing the design pattern so as to correspond to a value allowed by the second design constraint when the design constraint is not fulfilled.

Pattern generation method, computer-readable recording medium, and semiconductor device manufacturing method

A pattern dimension calculation method according to one embodiment calculates a taper shape of a mask member used as a mask when a circuit pattern is processed in an upper layer of the circuit pattern formed on a substrate. The method calculates an opening angle facing the mask member from a shape prediction position on the circuit pattern on the basis of the taper shape. The method calculates a dimension of the circuit pattern according to the opening angle formed at the shape prediction position.

Pattern dimension calculation method and computer program product

A pattern generating method includes: extracting, from a shape of a pattern generated on a substrate, a contour of the pattern shape; setting evaluation points as verification points for the pattern shape on the contour; calculating curvatures on the contour in the evaluation points; and verifying the pattern shape based on whether the curvatures satisfy a predetermined threshold set in advance.

Pattern generating method, method of manufacturing semiconductor device, computer program product, and pattern-shape-determination-parameter generating method

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Kanagawa, Japan

Hiromitsu Mashita