Fu-Cheng Wang

This inventor holds 12 USPTO granted patents and 3 published patent applications. Top assignee: National Semiconductor Corporation. Active years: 2002-2012.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Fu-Cheng Wang. Retrieved from https://idiyas.com/inventor/fu-cheng-wang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 12 (Patent Applications = 3)

% Patents Active = 66.7

Average Co-Inventor Count = 2.7

ph-index = 9

Forward Citations = 413(Granted Patents)

Location History:

Sunnyvale, CA (US) (2002 - 2003)
San Jose, CA (US) (2004 - 2012)

Company Filing History:

12 out of 4,791

National Semiconductor Corporation

patents

Years Active: 2002-2012

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12 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8129262 - Fabrication of field-effect transistor with vertical body-material dopant profile tailored to alleviate punchthrough and reduce current leakage (2012-03-06),

2. 7879669 - Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length (2011-02-01),

3. 7785971 - Fabrication of complementary field-effect transistors with vertical body-material dopant profiles tailored to alleviate punchthrough and reduce current leakage (2010-08-31),

4. 7701005 - Semiconductor structure in which like-polarity insulated-gate field-effect transistors have multiple vertical body dopant concentration maxima and different halo pocket characteristics (2010-04-20),

5. 7700980 - Structure and fabrication of field-effect transistor for alleviating short-channel effects (2010-04-20),

6. 7595244 - Fabrication of like-polarity insulated-gate field-effect transistors having multiple vertical body dopant concentration maxima and different halo pocket characteristics (2009-09-29),

7. 7145191 - P-channel field-effect transistor with reduced junction capacitance (2006-12-05),

8. 6797576 - Fabrication of p-channel field-effect transistor for reducing junction capacitance (2004-09-28),

9. 6599804 - Fabrication of field-effect transistor for alleviating short-channel effects (2003-07-29),

10. 6566204 - Use of mask shadowing and angled implantation in fabricating asymmetrical field-effect transistors (2003-05-20),

11. 6548842 - Field-effect transistor for alleviating short-channel effects (2003-04-15),

12. 6461932 - Semiconductor trench isolation process that utilizes smoothening layer (2002-10-08),

Title: Top Inventor in San Jose

Introduction: Shan Liu is a prominent inventor based in San Jose, California. He has made significant contributions to his field and is recognized for his innovative ideas and solutions.

Latest Patents: Shan Liu holds several patents that showcase his expertise and creativity in technology.

Career Highlights: Throughout his career, Liu has achieved numerous milestones that highlight his dedication and impact in the industry.

Collaborations: He has worked with various companies and institutions, fostering partnerships that enhance his work and broaden his influence.

Conclusion: Shan Liu continues to be a leading figure in innovation, inspiring others with his work and vision.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

3 patents pending: