Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length

Abstract

At least one source/drain zone (or) of an enhancement-mode insulated-gate field-effect transistor (or) is provided with graded junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each graded junction source/drain zone contains a main portion (M,M,M, orM) and a more lightly doped lower portion (L,L,L, orL) underlying, and vertically continuous with, the main portion. The magnitudes of the threshold voltages of a group of such transistors fabricated under the same post-layout fabrication process conditions so as to be of different channel lengths reach a maximum absolute value Vwhen the channel length is at a value L, are at least 0.03 volt less than Vwhen the channel length is approximately 0.3 μm greater than L, and materially decrease with increasing channel length when the channel length is approximately 1.0 μm greater than L.