National Semiconductor Corporation

Fu-Cheng Wang

Constantin Bulucea

Prasad Chaparala

Chih Sieh Teng

Chin-Miin Shyu

Fabrication of an insulated-gate field-effect transistor () entails separately introducing three body-material dopants, typically through an opening in a mask, into body material () of a semiconductor body so as to reach respective maximum dopant concentrations at three different vertical locations in the body material. A gate electrode () is subsequently defined after which a pair of source/drain zones (and), each having a main portion (M orM) and a more lightly doped lateral extension (E orE), are formed in the semiconductor body. An anneal is performed during or subsequent to introduction of semiconductor dopant that defines the source/drain zones. The body material is typically provided with at least one more heavily doped halo pocket portion (and) along the source/drain zones. The vertical dopant profile resulting from the body-material dopants alleviates punchthrough and reduces current leakage.

Fabrication of field-effect transistor with vertical body-material dopant profile tailored to alleviate punchthrough and reduce current leakage

At least one source/drain zone (or) of an enhancement-mode insulated-gate field-effect transistor (or) is provided with graded junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each graded junction source/drain zone contains a main portion (M,M,M, orM) and a more lightly doped lower portion (L,L,L, orL) underlying, and vertically continuous with, the main portion. The magnitudes of the threshold voltages of a group of such transistors fabricated under the same post-layout fabrication process conditions so as to be of different channel lengths reach a maximum absolute value Vwhen the channel length is at a value L, are at least 0.03 volt less than Vwhen the channel length is approximately 0.3 &#x3bc;m greater than L, and materially decrease with increasing channel length when the channel length is approximately 1.0 &#x3bc;m greater than L.

Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length

Fabrication of complementary first and second insulated-gate field-effect transistors (orandor) from a semiconductor body entails separately introducing (i) three body-material dopants into the body material () for the first transistor so as to reach respective maximum dopant concentrations at three different locations in the first transistor's body material and (ii) two body-material dopants into the body material () for the second transistor so as to reach respective maximum dopant concentrations at two different locations in the second transistor's body material. Gate electrodes (orandor) are subsequently defined after which source/drain zones (orandor) are formed in the semiconductor body. The vertical dopant profiles resulting from the body-material dopants alleviate punchthrough and reduce current leakage.

Fabrication of complementary field-effect transistors with vertical body-material dopant profiles tailored to alleviate punchthrough and reduce current leakage

Each of a pair of differently configured like-polarity insulated-gate field-effect transistors (orandor) in a semiconductor structure has a channel zone of semiconductor body material, a gate dielectric layer overlying the channel zone, and a gate electrode overlying the gate dielectric layer. For each transistor, the net dopant concentration of the body material reaches multiple local subsurface maxima below a channel surface depletion region and below largely all gate-electrode material overlying the channel zone. The transistors have source/drain zones (or) of opposite conductivity type to, and halo pocket portions of the same conductivity type as, the body material. One pocket portion (or) extends along both source/drain zones of one of the transistors. Another pocket portion (or) extends largely along only one of the source/drain zones of the other transistor so that it is asymmetrical.

Semiconductor structure in which like-polarity insulated-gate field-effect transistors have multiple vertical body dopant concentration maxima and different halo pocket characteristics

Each of a pair of like-polarity IGFETs (orandor) has a channel zone (or) situated in body material (). Short-channel effects are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (andorand) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &#x3bc;m deep into the body material but not more than 0.4 &#x3bc;m deep into the body material. A pocket portion (or) extends along both source drain zones of one of the IGFETs. A pocket portion (or) extends largely along only one of the source/drain zones of the other IGFET so that it is an asymmetrical device.

Structure and fabrication of field-effect transistor for alleviating short-channel effects

Fabrication of two differently configured like-polarity insulated-gate field-effect transistors (orandor) entails introducing multiple body-material semiconductor dopants of the same conductivity type into a semiconductor body. Gate electrodes (or) are defined such that each body-material dopant reaches a maximum concentration below the channel surface depletion regions, below all gate-electrode material overlying the channel zones (or), and at a different depth than each other body-material dopant. The transistors are provided with source/drain zones (or) of opposite conductivity type to, and with halo pocket portions of the same conductivity type as, the body-material dopants. One pocket portion (or) extends along both source/drain zones of one of the transistors. Another pocket portion (or) extends largely along only one of the source/drain zones of the other transistor so that it is asymmetrical.

Fabrication of like-polarity insulated-gate field-effect transistors having multiple vertical body dopant concentration maxima and different halo pocket characteristics

The source/drain zones (andorand) of a p-channel IGFET (or) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each source/drain zone contains a main portion (M,M,M, orM) and a more lightly doped lower portion (L,L,L, orL) underlying, and vertically continuous with, the main portion.

P-channel field-effect transistor with reduced junction capacitance

An IGFET ( or ) has a channel zone ( or ) situated in body material ( ). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones ( and or and ) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.1 &mgr;m deep into the body material. The source/drain zones ( and or and ) of a p-channel IGFET ( or ) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed.

Fabrication of p-channel field-effect transistor for reducing junction capacitance

Short-channel threshold voltage roll-off and punchthrough in an IGFET ( or ) having a channel zone ( or ) situated in body material ( ) are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones ( and or and ) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.4 &mgr;m deep into the body material.

Fabrication of field-effect transistor for alleviating short-channel effects

To furnish an IGFET ( or ) with an asymmetrically doped channel zone ( or ), a mask ( ) is provided over a semiconductor body and an overlying electrically insulated gate electrode ( P or P). Ions of a semiconductor dopant species are directed toward an opening ( ) in the mask from two different angular orientations along paths that originate laterally beyond opposite respective opening-defined sides of the mask. The location and shape of the opening are controlled so that largely only ions impinging from one of the angular orientations enter the intended location for the channel zone. Ions impinging from the other angular orientation are shadowed by the mask from entering the channel zone location. Although the ions impinging from this other angular orientation do not significantly dope the channel zone location, they normally enter the semiconductor body elsewhere, e.g., the intended location for the channel zone of another IGFET.

Use of mask shadowing and angled implantation in fabricating asymmetrical field-effect transistors

An IGFET ( or ) has a channel zone ( or ) situated in body material ( ). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones ( and or and ) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.4 &mgr;m deep into the body material.

Field-effect transistor for alleviating short-channel effects

A trenched-isolated semiconductor structure is created by a process that entails forming a patterned trench ( ) along an upper surface of a semiconductor body ( ). A dielectric layer ( ) is provided over the upper semiconductor surface. The dielectric layer is covered with a smoothening layer ( ) whose upper surface is smoother than the upper surface of the dielectric layer. The smoothening layer is removed starting from its upper surface. During the removal of the smoothening layer, upward-protruding material of the dielectric layer progressively becomes exposed and is also removed. As a result, the remainder of dielectric layer has a smoother upper surface than the initial upper surface of the dielectric layer.

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Fu-Cheng Wang