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For the Inventor, By the Inventor

Queensbury, NY, United States of America

Andy C Wei

USPTO Granted Patents = 56 

Average Co-Inventor Count = 3.4

ph-index = 11

Forward Citations = 582(Granted Patents)

DiyaCoin DiyaCoin = 0.39 


Inventors with similar research interests:


Company Filing History:

goldMedal56 out of 5,671 
 
Globalfoundries Inc.
 patents

Years Active: 2013-2018

where 'Filed Patents' based on already Granted Patents

56 patents (USPTO):
1. 9899268 - Cap layer for spacer-constrained epitaxially grown material on fins of a FinFET device (2018-02-20),
2. 9852984 - Cut first alternative for 2D self-aligned via (2017-12-26),
3. 9825031 - Methods of forming a high-k contact liner to improve effective via separation distance and the resulting devices (2017-11-21),
4. 9704973 - Methods of forming fins for FinFET semiconductor devices and the selective removal of such fins (2017-07-11),
5. 9660075 - Integrated circuits with dual silicide contacts and methods for fabricating same (2017-05-23),
6. 9583351 - Inverted contact (2017-02-28),
7. 9520395 - FinFET devices comprising a dielectric layer/CMP stop layer/hardmask/etch stop layer/gap-fill material stack (2016-12-13),
8. 9515026 - Methods of forming alignment marks and overlay marks on integrated circuit products employing FinFET devices and the resulting alignment/overlay mark (2016-12-06),
9. 9508850 - Epitaxial block layer for a fin field effect transistor device (2016-11-29),
10. 9502293 - Self-aligned via process flow (2016-11-22),
11. 9490340 - Methods of forming nanowire devices with doped extension regions and the resulting devices (2016-11-08),
12. 9437713 - Devices and methods of forming higher tunability FinFET varactor (2016-09-06),
13. 9431512 - Methods of forming nanowire devices with spacers and the resulting devices (2016-08-30),
14. 9425097 - Cut first alternative for 2D self-aligned via (2016-08-23),
15. 9412655 - Forming merged lines in a metallization layer by replacing sacrificial lines with conductive lines (2016-08-09),

Title: Innovations by Andy C Wei: A Pioneer in Semiconductor Patents

Introduction: Andy C Wei, based in Queensbury, NY, is a prolific inventor with a remarkable portfolio of 56 patents. With a focus on cutting-edge semiconductor technologies, Andy has made significant contributions through his innovative work, notably at GlobalFoundries Inc. His expertise in the field continues to shape advancements in the semiconductor industry.

Latest Patents: Among Andy's latest patents is the "Cap layer for spacer-constrained epitaxially grown material on fins of a FinFET device." This method involves forming fins in a semiconductor substrate and utilizing a fin spacer to support the growth of epitaxial materials. This technology ensures the protection of the materials during manufacturing processes, showcasing Andy's commitment to enhancing device reliability.

Another notable patent is the "Cut first alternative for 2D self-aligned via." This innovative method provides a lithographic technique for cutting a line before its definition, optimizing the fabrication process for semiconductor devices. Both patents highlight Andy's ingenuity and the practical applications of his work in the semiconductor realm.

Career Highlights: Andy C Wei has established himself as an influential figure at GlobalFoundries Inc., where he plays a crucial role in developing semiconductor technologies. His extensive patent portfolio not only underscores his innovative capabilities but also reflects his dedication to advancing the industry forward.

Collaborations: Throughout his career, Andy has collaborated with talented professionals such as Guillaume Bouche and Shao Ming Koh. These partnerships demonstrate his ability to work alongside other experts in the field, fostering an environment of creativity and innovation.

Conclusion: Andy C Wei's contributions to semiconductor technology through his patents at GlobalFoundries Inc. illustrate the profound impact that dedicated inventors can have on the industry. His innovative approaches to complex challenges pave the way for future advancements, solidifying his status as a key player in semiconductor developments.

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